Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

2.6. Design Synthesis

The Intel® Quartus® Prime compiler's Analysis & Elaboration module analyzes your complete design source files, such as standards-compliant Verilog HDL (.v), VHDL (.vhd), SystemVerilog (.sv), and the Verilog Quartus Mapping (.vqm) generated from other EDA tools, and constraint files (.sdc or .rtlsdc) and provides an unmodified view of your design early in the compilation flow. The SDC-on-RTL constraints are applied to the elaborated netlist.

In the Synthesis stage, the compiler synthesizes and translates your design files into an atom netlist for mapping to device resources. During synthesis, timing constraints that were read during elaboration are propagated to the synthesized atom netlist.

CAUTION:

Starting from the Intel® Quartus® Prime Pro Edition software version 23.3, the compiler cannot synthesize schematic Block Design File (.bdf). You must convert it to an acceptable format, such as Verilog or VHDL using only the Intel® Quartus® Prime Standard Edition (not possible with the Pro Edition) command quartus_map as shown in the following:

  • To convert your .bdf file to Verilog Design File (.v):
    quartus_map <project_name> --convert_bdf_to_verilog=<bdf_file_name>
  • To convert your .bdf file to VHDL Design File (.vhd):
    quartus_map <project_name> --convert_bdf_to_vhdl=<bdf_file_name>

Synthesis examines the logical completeness and consistency of the design, and checks for boundary connectivity and syntax errors. Synthesis also minimizes and optimizes design logic. For example, synthesis infers D flip flops, latches, and state machines from "behavioral" languages, such as Verilog HDL, VHDL, and SystemVerilog. Synthesis may replace operators, such as + or –, with modules from the Intel® Quartus® Prime IP library, when advantageous. During synthesis, the Compiler may change or remove user logic and design nodes. Intel® Quartus® Prime synthesis minimizes gate count, removes redundant logic, and ensures efficient use of device resources.

At the end of synthesis, the Compiler generates an atom netlist. Atom refers to the most basic hardware resource in the FPGA device. Atoms include logic cells organized into look-up tables, D flip flops, I/O pins, block memory resources, DSP blocks, and the connections between the atoms. The atom netlist is a database of the atom elements that design synthesis requires to implement the design in silicon.

Figure 37. Design Synthesis