Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
Document Table of Contents
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2.8.2.1.1. Analyzing Failing Paths with Snapshot Viewer

  1. To run the Plan, Place, or Route stage of the Fitter, double-click the stage in the Compilation Dashboard.
  2. After the stage completes, click the Snapshot Viewer icon for that stage in the Compilation Dashboard. The Snapshot Viewer opens.
    Figure 90. Snapshot Viewer Icon
  3. Under Analyze Failing Paths, click List Top Failing Paths.
    Figure 91. List Top Failing Paths
  4. In Snapshot Selections, select the failing path for analysis.
    Figure 92. Snapshot Selections
  5. Under Select Failing Path to Analyze, click Show Full Timing Path in the Chip View. The path displays and highlights in the Chip Planner for further analysis.
  6. Under Select Failing Path to Analyze, click Show Full Timing Path in Schematic. The path displays and highlights in RTL Viewer for further analysis.
    Figure 93. Show Full Timing Path in Schematic
  7. Under Select Failing Path to Analyze, click View Path Characteristics. The path loads in the Timing Analyzer for further analysis.
    Figure 94. View Path Characteristics in Timing Analyzer