Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
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Document Table of Contents
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2.7.2.1. Plan Stage Reports

The Plan stage reports describe the I/O, interface, and control signals discovered during the periphery planning stage of the Fitter.
Figure 76. Plan Stage Reports ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)

For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, the Plan stage includes the Global & Other Fast Signals Summary report that allows you to verify which clocks the Compiler promotes to global clocks. Clock planning occurs after the Plan stage for Intel® Stratix® 10 and Intel Agilex® 7 designs.

NoC Connectivity Report

For Intel Agilex® 7 M-Series FPGAs only, the NoC Connectivity Report provides information on connections between NoC initiators and targets in the implemented design, and their associated base addresses. Use this report to verify that the implementation of connection and attribute assignments are correct. The table in this report contains a row for each initiator to target connection. Additional rows may report any unconnected NoC elements. The following columns report data:

  • Group—displays which NoC group the connection is assigned to.
  • Status—displays whether the row is for connected or unconnected elements.
  • Initiator—lists the NoC initiator elements.
  • Target—lists the NoC target elements.
  • Address—displays the hexadecimal base address for each connection

NoC Performance Report

For Intel Agilex® 7 M-Series FPGAs only, reports the user-requested read and write bandwidths, as well as the minimum latency of NoC request and response transactions.

The latencies in this report are based on the minimum structural latency with respect to the initiator and target placement. These latencies are for the NoC portion of the path only. These latencies do not include any latency of, for instance, external memory access. Nor do these latencies account for potential delay due to congestion on the NoC. You can achieve lower minimum structural latency by placing the NoC initiators and targets closer together.