Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
Document Table of Contents

2.15.1.3. Verilog HDL Configuration

Verilog HDL configuration is a set of rules that specify the source code for particular instances. Verilog HDL configuration allows you to perform the following tasks:
  • Specify a library search order for resolving cell instances (as does a library mapping file).
  • Specify overrides to the logical library search order for specified instances.
  • Specify overrides to the logical library search order for all instances of specified cells.