Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
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2.8.3. Validating Periphery (I/O) after the Plan Stage

The Compiler begins periphery placement during the Plan stage, and reports data about periphery elements, such as I/O pins and PLLs. After the Plan stage, view the Compilation Report to evaluate the placement of periphery elements before proceeding to the next compilation stage.
Figure 100. Plan Stage Periphery Placement Message
  1. In the Compilation Dashboard, click the Plan stage.
  2. In the Compilation Report, under the Plan Stage folder, click the Input Pins, Output Pins, I/O Bank Usage, PLL Usage Summary, or other reports. Verify attributes of the I/O pins, such as the physical pin location, I/O standards, and PLL placement.
    Figure 101. Input Pins Report
  3. For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, click Global & Other Fast Signals Summary report to verify which clocks the Compiler promotes to global clocks. Clock planning occurs after the Plan stage for Intel® Stratix® 10 and Intel Agilex® 7 designs.
    Figure 102. Global & Other Fast Signals Report Shows Clock Promotion ( Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs)