Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
Document Table of Contents

2.14.1. Compiler Optimization Modes

To apply the compiler optimization settings, click Assignments > Settings > Compiler Settings.
Alternatively, you can apply the optimization settings using the OPTIMIZATION_MODE QSF. For example:
set_global_assignment -name OPTIMIZATION_MODE "Aggressive Area"
The default value for OPTIMIZATION_MODE is "Balanced". For all other values, refer to the Optimization Modes table.

You can enable one of the following optimization modes to focus the Compiler's optimization effort. The settings compilation mode you select affects synthesis and fitting results.

To select an optimization mode, start with the Balanced setting. This mode is appropriate for many designs and provides an implementation balanced between optimization and compile time. If this setting does not meet your goals, you can try different optimization modes depending on your requirements.

If your design requires additional performance compared to the Balanced setting, use the High performance effort setting that enables additional timing optimizations during the fitting stage. You can achieve additional performance using the Superior performance setting that further enables additional timing optimizations during the Synthesis stage. However, these synthesis optimizations may result in increased logic area, negatively impacting designs with high utilization. Both settings increase compile time.

Alternatively, use the Aggressive Area setting to reduce logic area at the potential expense of performance. Similarly, use the Aggressive power setting to reduce dynamic power at the potential expense of performance.

If your design has difficulty routing successfully, the settings Optimize netlist for routability, High placement routability effort, and High packing routability effort offer a variety of optimizations to improve routability. Which optimizations work best is design-dependent, so try each if you encounter routability issues.

Finally, use Aggressive Compile Time and Fast Functional Test settings to reduce compile time. These settings reduce performance but may be helpful early in a design cycle when only functionality is being verified.

Table 31.  Optimization Modes (Compiler Settings Page)

Optimization Mode

QSF Value

Description

Implications

Balanced

(normal flow)
Balanced

The Compiler optimizes synthesis for balanced implementation that respects timing constraints.

The default setting that produces a balance between optimization effort and compile time.

High performance effort

High Performance Effort

The Compiler increases the timing optimization effort during placement and routing, and enables timing-related Physical Synthesis optimizations (per register optimization settings).

Increases compilation time for better performance compared to Balanced setting.
High performance with maximum placement effort High Performance With Maximum Placement Effort Enables the same Compiler optimizations as High performance effort, with additional placement optimization effort. Increases compilation time for better performance compared to High performance effort setting.
High performance with aggressive power effort High Performance With Aggressive Power Effort Enables the same Compiler optimizations as High performance effort, while performing additional optimizations to reduce dynamic-power. Increases compilation time for lower power compared to High performance effort setting.
Superior performance Superior Performance Enables the same Compiler optimizations as High performance effort, and adds more optimizations during Analysis & Synthesis to maximize design performance with a potential increase to logic area. Increases compilation time for better performance compared to High performance effort setting. If design utilization is very high, this mode can cause difficulty in fitting, which can also negatively affect overall optimization quality.
Superior performance with maximum placement effort Superior Performance With Maximum Placement Effort Enables the same Compiler optimizations as Superior performance, with additional placement optimization effort. Increases compilation time for better performance compared to Superior performance setting.
Aggressive Area (reduces performance) Agressive Area

The Compiler makes aggressive effort to reduce the device area required to implement the design at the potential expense of design performance.

Reduces performance for reduced area compared to Balanced setting.
High placement routability effort High Placement Routability Effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time reducing routing utilization, which can improve routability and also saves dynamic power. Increases compilation time for better routability compared to Balanced setting.
High packing routability effort High Packing Routability Effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time packing registers, which can improve routability and also saves dynamic power. Increases compilation time for better routability compared to Balanced setting.
Optimize netlist for routability Optimize Netlist for Routability The Compiler implements netlist modifications to increase routability at the possible expense of performance. Increases compilation time for better routability compared to Balanced setting.

Aggressive power

(reduces performance)
Agressive Power

Makes aggressive effort to optimize synthesis for low power. The Compiler further reduces the routing usage of signals with the highest specified or estimated toggle rates, saving additional dynamic power but potentially affecting performance.

Reduces performance for lower power compared to Balanced setting.

Aggressive Compile Time (reduces performance)

Aggressive Compile Time

Especially useful during early design iterations, this mode reduces the compilation run time by 30% (on average) at the expense of design fMAX of 15% (on average). Run time reduction occurs through reduced effort and fewer performance optimizations. This mode also disables some detailed reporting functions.

This mode produces the fastest full-flow timing estimation with an approximate correlation to the high-effort modes.

  • This mode reduces performance.
  • Reduced effort levels can cause no-fits, especially on highly congested designs. Mitigate this potential by either partitioning and constraining the placement of congested parts of design, or by using a high effort or routability mode
  • This mode may not identify the same critical paths as a full-effort compile (similar to Compiler seed-effects).
  • This mode disables some detailed reporting functions and enables .qsf settings that cannot be overridden by other .qsf settings.
Fast Functional Test (hold-timing optimization only) Fast Functional Test

This mode produces a .sof bitstream file that you can use for on-board functional testing with minimal compile time. This mode further reduces compile time beyond Aggressive Compile Time mode by limiting timing optimizations to only those for hold requirements.

  • Reduced effort levels can cause no-fits, especially on highly congested designs. Mitigate this potential by either partitioning and constraining the placement of congested parts of design, or by using a high effort or routability mode. Refer to the Creating a Partition topic in this document and the Intel Quartus Prime Pro Edition User Guide: Design Constraints
  • This mode can require clock speeds outside the lock range of the PLL Intel FPGA IP. Mitigate this effect by using the adjust_pll ECO command to update the PLL IP after fitting.
  • This mode disables some detailed reporting functions and enables .qsf settings that cannot be overridden by other .qsf settings.
Note: If you enable extended optimization modes for Design Space Explorer II by use of .qsf assignments, and then subsequently open the Compiler Settings tab for that project revision, the Compiler Settings tab indicates that the extended optimization mode reverts to one of the Compiler Settings tab Optimization Modes.