Quartus® Prime Pro Edition User Guide: Design Compilation
ID
683236
Date
9/30/2024
Public
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1.1. Compilation Overview
1.2. Design Analysis & Elaboration
1.3. Design Synthesis
1.4. Design Place and Route
1.5. Incremental Optimization Flow
1.6. Fast Forward Compilation Flow
1.7. Full Compilation Flow
1.8. HSSI Dual Simplex IP Generation Flow
1.9. Exporting Compilation Results
1.10. Clearing Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Viewing Quartus Database File Information
1.15. Understanding the Design Netlist Infrastructure
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files
1.17. Using the Node Finder
1.18. Synthesis Language Support
1.19. Synthesis Settings Reference
1.20. Fitter Settings Reference
1.21. Design Compilation Revision History
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
1.12.6.1. Enabling or Disabling Fractal Synthesis
For Stratix® 10 and Agilex™ family devices, fractal synthesis optimization runs automatically for small multipliers (any A*B statement in Verilog HDL or VHDL where bit-width of the operands is 7 or less). You can also disable automatic fractal synthesis for small multipliers for these devices using either of the following methods:
- In RTL, set the DSP multstyle, as "Multstyle Verilog HDL Synthesis Attribute" describes. For example:
(* multstyle = "dsp" *) module foo(...); module foo(..) /* synthesis multstyle = "dsp" */;
- In the .qsf file, add as an assignment as follows:
set_instance_assignment -name DSP_BLOCK_BALANCING_IMPLEMENTATION \ DSP_BLOCKS -to r
In addition, for Stratix® 10, Arria® 10, Cyclone® 10 GX, and Agilex™ family devices, you can enable fractal synthesis globally or for specific multipliers with the Fractal Synthesis GUI option or the corresponding FRACTAL_SYNTHESIS .qsf assignment:
- In RTL, use altera_attribute as follows:
(* altera_attribute = "-name FRACTAL_SYNTHESIS ON" *)
- In the .qsf file, add as an assignment as follows:
set_global_assignment -name FRACTAL_SYNTHESIS ON -entity <module name>
In the user interface, follow these steps:
- Click Assignments > Assignment Editor.
- Select Fractal Synthesis for Assignment Name, On for the Value, the arithmetic-intensive entity name for Entity, and an instance name in the To column. You can enter a wildcard (*) for To to assign all instances of the entity.
Figure 111. Fractal Synthesis Assignment in Assignment Editor
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