Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Design Analysis & Elaboration 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. HSSI Dual Simplex IP Generation Flow 1.9. Exporting Compilation Results 1.10. Clearing Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Viewing Quartus Database File Information 1.15. Understanding the Design Netlist Infrastructure 1.16. Using Synopsys* Design Constraint (SDC) on RTL Files 1.17. Using the Node Finder 1.18. Synthesis Language Support 1.19. Synthesis Settings Reference 1.20. Fitter Settings Reference 1.21. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard
1.2. Design Analysis & Elaboration x
1.2.1. Locating Design Elements 1.2.2. Using the RTL Analyzer
1.2.1. Locating Design Elements x
1.2.1.1. Copying Hierarchy Path Names
1.2.2. Using the RTL Analyzer x
1.2.2.1. Sweep Hints Viewer 1.2.2.2. Object Set Console 1.2.2.3. Module Interfaces 1.2.2.4. Bundled Instances 1.2.2.5. Auto-hide Unconnected Pins 1.2.2.6. Filtering Ports and Nets 1.2.2.7. Expand Connections
1.3. Design Synthesis x
1.3.1. Preparing for Design Synthesis 1.3.2. Running Synthesis 1.3.3. Post-Synthesis Static Timing Analysis (STA) 1.3.4. Viewing Synthesis Reports
1.3.2. Running Synthesis x
1.3.2.1. Preserving Registers During Synthesis 1.3.2.2. Preserving Signals for Monitoring and Debugging
1.3.4. Viewing Synthesis Reports x
1.3.4.1. Viewing IP Core License Data 1.3.4.2. Viewing Synthesis Dynamic Report
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Disabling or Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Congestion Hotspot Summary Report 1.4.2.3.2. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.7. Full Compilation Flow x
1.7.1. Full Compilation Flow with Temporary Optimization Mode
1.9. Exporting Compilation Results x
1.9.1. Exporting a Version-Compatible Compilation Database 1.9.2. Importing a Version-Compatible Compilation Database 1.9.3. Creating a Design Partition 1.9.4. Exporting a Design Partition 1.9.5. Reusing a Design Partition
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Allow Register Retiming 1.12.3. Automatic Gated Clock Conversion 1.12.4. Enable Intermediate Fitter Snapshots 1.12.5. Fast Preserve Option 1.12.6. Fractal Synthesis Optimization
1.12.6. Fractal Synthesis Optimization x
1.12.6.1. Enabling or Disabling Fractal Synthesis
1.14. Viewing Quartus Database File Information x
1.14.1. QDB File Attribute Types
1.15. Understanding the Design Netlist Infrastructure x
1.15.1. DNI Netlist Five-Box Data Model
1.15.1. DNI Netlist Five-Box Data Model x
1.15.1.1. Use Case Examples
1.15.1.1. Use Case Examples x
1.15.1.1.1. Scripting Routine Tasks Using Tcl Commands 1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.16.1. Registering the SDC-on-RTL SDC File 1.16.2. Applying the SDC-on-RTL Constraints 1.16.3. Inspecting SDC-on-RTL Constraints 1.16.4. Creating Constraints in SDC-on-RTL SDC Files 1.16.5. Using Entity-Based SDC-on-RTL Constraints 1.16.6. Types of SDC Files Used in the Quartus® Prime Software
1.16.4. Creating Constraints in SDC-on-RTL SDC Files x
1.16.4.1. Example: Using SDC-on-RTL Features
1.16.4.1. Example: Using SDC-on-RTL Features x
1.16.4.1.1. SDC-on RTL Example: Targeting Pins of Top-level Instances 1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells 1.16.4.1.3. SDC-on RTL Example: Targeting Pins Using Wildcards 1.16.4.1.4. SDC-on RTL Example: Applying Constraints at Deeper Hierarchies
1.16.5. Using Entity-Based SDC-on-RTL Constraints x
1.16.5.1. Entity-based SDC-on-RTL Constraints Example
1.17. Using the Node Finder x
1.17.1. Node Finder Settings Reference
1.18. Synthesis Language Support x
1.18.1. Verilog and SystemVerilog Synthesis Support 1.18.2. VHDL Synthesis Support
1.18.1. Verilog and SystemVerilog Synthesis Support x
1.18.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.18.1.2. Design Libraries 1.18.1.3. Verilog HDL Configuration 1.18.1.4. Initial Constructs and Memory System Tasks 1.18.1.5. Verilog HDL Macros
1.18.1.3. Verilog HDL Configuration x
1.18.1.3.1. Hierarchical Design Configurations
1.18.2. VHDL Synthesis Support x
1.18.2.1. VHDL Input Settings (Settings Dialog Box) 1.18.2.2. VHDL Standard Libraries and Packages 1.18.2.3. VHDL wait Constructs 1.18.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.19. Synthesis Settings Reference x
1.19.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Compilation on a Compute Farm 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Running the ECO Compilation Flow 2.2.4. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time x
2.3.1. Using Precompiled Component Generation 2.3.2. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
2.3.1. Using Precompiled Component Generation x
2.3.1.1. Enabling Precompiled Components Generation 2.3.1.2. Precompiled Component Generation Flow
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.21. Design Compilation Revision History

This document has the following revision history.
Document Version Quartus® Prime Version Changes
2024.09.30 24.3
  • Added new Locating Design Elements topic.
  • Revised Example: Using SDC-on-RTL Features section.
  • Revised Design Analysis & Elaboration for precompiled components.
  • Revised Viewing Synthesis Reports for IP Cores Summary report data.
  • Added Viewing IP Core License Data topic.
  • Moved/retitled Understanding the Design Netlist Infrastructure topic.
  • Updated Entity-based SDC-on-RTL Constraints Example.
  • Revised Example: Using SDC-on-RTL Features section
  • Added new Copying Hierarchy Path Names topic.
  • Updated Node Finder Settings Reference topic interface search filters.
2024.07.08 24.2
  • Updated throughout to reflect support for Agilex™ 5 devices.
  • Updated Compilation Overview for latest device-specific compilation stages.
  • Revised Using the Node Finder.
  • Added note to Sweep Hints Viewer topic.
  • Revised search order in Verilog and SystemVerilog Synthesis Support topic.
  • Moved Design Netlist Infrastructure topic under Compilation Overview and revised wording.
  • Moved Precompiled Component (PCC) Generation Stage topic under Compiler Optimization Techniques.
  • Moved Compilation on a Compute Farm topic under Compiler Optimization Techniques.
2024.04.01 24.1
  • Added Precompiled Component (PCC) flow to Compilation Flows.
  • Updated images and added information about the "RTL Analysis Debug Mode" in Analysis & Elaboration Flow.
  • Updated the images and enhanced the information in Using the Node Finder.
  • Revised the information in Fast Forward Details Report.
  • Added Precompiled Component (PCC) Generation Flow.
2023.12.04 23.4
  • Enhanced the Compiler Optimization Modes topic with additional information.
  • Updated file properties image in Registering the SDC-on-RTL SDC File and Using SDC-on-RTL Features.
  • In Design Synthesis, added information about converting .bdf to .v or .vhd file, and updated the image.
  • Renamed DNI-Based Compilation Flow as Analysis & Elaboration Flow.
  • Added information about Early Timing Analysis flow in Compilation Overview.
  • Reorganized DNI-Based Analysis & Elaboration Flow and Early Timing Analysis After Design Synthesis sections.
  • Renamed DNI-Based Node Finder as Using the Node Finder
  • Added an image for Property Viewer showing constraints in Exploring the RTL Analyzer.
  • Reorganized most of the topics under Design Netlist Infrastructure and moved them into relevant sections of this chapter.
  • Removed the term "DNI" in the title and content of the following topics:
    • Use Case Examples
    • Scripting Routine Tasks Using Tcl Commands
    • Traversing the Design Netlist Using Tcl Commands
  • Revised the information and image in Design Synthesis.
  • Added information about SDC-on-RTL file in Running Synthesis.
  • Revised the image, added a note for "Parameter Settings by Entity Instance" and added information about SDC constraints in Viewing Synthesis Reports.
  • Revised the existing information in Concurrent Analysis During Synthesis or Fitting.
  • Added a note about version compatibility in Importing a Version-Compatible Compilation Database, and Exporting a Design Partition.
  • Renamed the topic Compilation Monitoring as Compilation Monitoring Mode and revised the topic entirely.
  • Revised Enable Intermediate Fitter Snapshots with additional information.
  • Added Preparing for Design Synthesis.
  • Removed Early Timing Analysis After Design Synthesis and merged its information with Post-Synthesis Static Timing Analysis (STA).
2023.10.02 23.3
  • Enhanced the instructions and removed "Beta" in Design Netlist Infrastructure and Exploring the RTL Analyzer.
  • Made minor revisions to the description in Object Set Console.
  • Updated "Viewing Unbundled Instances" section in Bundled Instances.
  • Completely revised the instructions in Early Timing Analysis After Design Synthesis.
  • Made minor updates to Synopsys* Design Constraint (SDC) on RTL.
  • Completely updated "RTL Analyzer" section and added additional information about Constraints viewer in Inspecting SDC-on-RTL Constraints.
  • Added the following topics
    • Entity-Based SDC-on-RTL
    • Using SDC-on-RTL Features
    • DNI-Based Node Finder
  • Updated the commands and replaced SYN_SDC_FILE with SDC_FILE -read_during_post_syn_and_not_post_fit_timing_analysis in Post-Synthesis Static Timing Analysis (STA).
  • Replaced SYN_SDC_FILE in Types of SDC Files Used in the Quartus® Prime Software.
  • Reorganized the topics in the Design Compilation chapter per the DNI-based compilation dashboard.
  • Updated the compilation dashboard image in the following topics:
    • Using the Compilation Dashboard
    • Concurrent Analysis During Synthesis or Fitting
    • Step 1: Run Register Retiming
    • Step 3: Run Fast Forward Compile
    • Fast Forward Compile By Hierarchy
  • Added description for "Number of Congested Nets" column in Global Router Congestion Hotspot Summary Report.
  • Revised the descriptions of optimization modes in Compiler Optimization Modes.
  • Removed the topic Connectivity Tracer.
  • Updated the "Hierarchical Project Structure" image along with its description in Compilation Hierarchy.
2023.04.03 23.1
  • In Design Netlist Infrastructure (Beta), updated the images and added a note about the incompatibilities between classic and DNI compilation flows.
  • In Exploring the RTL Analyzer (Beta), updated the images and improved their clarity.
  • Enhanced the Sweep Hints Viewer topic with additional information and images.
  • Enhanced the Inspecting SDC-on-RTL Constraints topic with additional information about Object Constraints viewer.
  • Revised the Object Set Console topic entirely.
  • Revised the Auto-hide Unconnected Pins topic entirely.
  • Renamed the topic Early Timing Analysis (Beta) to Early Timing Analysis After Design Synthesis (Beta) and revised the information and images.
  • Enhanced Applying the SDC-on-RTL Constraints with additional information about the Constraint Propagation Report.
  • Updated the images and revised some instructions in Post-Synthesis Static Timing Analysis (STA).
  • Updated the product family name to "Intel Agilex 7."
  • Revised description of Fitter (Finalize) command for latest physical synthesis optimizations.
2022.12.19 22.4
  • Added Filtering.
  • Added Expand Connections.
  • Revised Object Set Console with additional information and images.
2022.09.26 22.3
  • Added Early Timing Analysis (Beta).
  • Added Synopsys* Design Constraint (SDC) on RTL.
  • Added Registering the SDC-on-RTL SDC File.
  • Added Applying the SDC-on-RTL Constraints.
  • Added Managing SDC-on-RTL Constraints.
  • Added Writing Constraints in SDC-on-RTL SDC Files.
  • Added Post-synthesis Static Timing Analysis (STA).
  • Added Types of SDC Files Used in the Quartus® Prime Software.
  • Added Object Set Console.
  • Added Module Interfaces.
  • Added Connectivity Tracer.
  • Added DNI Use Case Examples.
  • Added Scripting Routine Tasks Using DNI Tcl Commands.
  • Added Traversing the DNI Netlist Using Tcl Commands.
  • Added Viewing Synthesis Dynamic Report.
  • Split the topic Instances Bundling and Auto-hiding Unconnected Pins into separate topics Bundled Instances and Auto-hide Unconnected Pins.
  • Revised Bundled Instances with additional information.
  • Revised images in Exploring the RTL Analyzer and Design Netlist Infrastructure (DNI).
2022.06.21 22.2
  • Added Design Netlist Infrastructure (DNI).
  • Added Exploring the RTL Analyzer.
  • Added Module Interfaces.
  • Added Instances Bundling and Auto-hiding Unconnected Pins.
2022.03.28 22.1
  • Added Compilation Monitoring.
  • Added Global Router Congestion Hotspot Summary Report.
  • Revised Full Compilation Flow.
  • Added Full Compilation Flow with Temporary Optimization Mode.
Level Two Title