Quartus® Prime Pro Edition User Guide: Design Compilation
ID
683236
Date
9/30/2024
Public
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1.1. Compilation Overview
1.2. Design Analysis & Elaboration
1.3. Design Synthesis
1.4. Design Place and Route
1.5. Incremental Optimization Flow
1.6. Fast Forward Compilation Flow
1.7. Full Compilation Flow
1.8. HSSI Dual Simplex IP Generation Flow
1.9. Exporting Compilation Results
1.10. Clearing Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Viewing Quartus Database File Information
1.15. Understanding the Design Netlist Infrastructure
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files
1.17. Using the Node Finder
1.18. Synthesis Language Support
1.19. Synthesis Settings Reference
1.20. Fitter Settings Reference
1.21. Design Compilation Revision History
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
Your HDL coding style can also affect the synthesis time. For example, if you want to infer RAM blocks from your code, you must follow the guidelines for inferring RAMs. If RAM blocks are not inferred properly, the software implements those blocks as registers.
If you are trying to infer a large memory block, the software consumes more resources on the FPGA. This can cause routing congestion and increases compilation time significantly. If you see high routing utilization in certain blocks, review the code for such blocks.