Intel® FPGA SDK for OpenCL™ Standard Edition: Best Practices Guide

ID 683176
Date 9/24/2018
Public
Document Table of Contents

2.5.2. Features of the Kernel Memory Viewer

Data movement is often a bottleneck in many algorithms. The kernel memory viewer in the High Level Design Report (report.html) shows you how the interprets the data connections across the memory system of your kernel. Use the Kernel Memory Viewer to help you identify data movement bottlenecks in your kernel design.

Also, some patterns in memory accesses can cause undesired arbitration in the load-store units (LSUs), which can affect the throughput performance of your kernel. Use the Kernel Memory Viewer to find where you might have unwanted arbitration in the LSUs.

The Kernel Memory Viewer has the following panes:
Memory List
The Memory List pane shows you a hierarchy of kernels, memories in that kernel, and the corresponding memory banks.

Clicking a memory name in the list displays a graphical representation of the memory in the Kernel memory viewer pane. Also, the line in your code where you declared the memory is highlighted in the Source Code pane.

Clearing a check box for a memory bank collapses that bank in the Kernel Memory Viewer pane, which can help you to focus on specific memory banks when you view a complex memory design. By default, all banks in kernel memory are selected and shown in the Kernel Memory Viewer pane.

Kernel Memory Viewer
The Kernel Memory Viewer pane shows you connections between loads and stores to specific logical ports on the banks in a memory system. The following types of nodes might be shown in the Kernel Memory Viewer pane, depending on the kernel memory system:
  • Memory node: The kernel memory.
  • Bank node: A bank in the memory. Only banks selected in the Memory List pane are shown. Select banks in the Memory List pane to help you focus on specific on memory banks when you view a complex memory design.
  • Port node: The logical port for a bank. There are three types of port:
    • R: A read-only port
    • W: A write-only port
    • RW: A read and write port
  • LSU node: A store (ST) or load (LD) node connected to the memory.
  • Arbitration node: An arbitration (ARB) node shows that LSUs compete for access to a shared port node,which can lead to stalls.
  • Port-sharing node: A port-sharing node (SHARE) shows that LSUs have mutually exclusive access to a shared port node, so the load-store units are free from stalls.

Hover over any node to view the attributes of that node.

Hover over an LSU node to highlight the path from the LSU node to all of the ports that the LSU connects to.

Hover over a port node to highlight the path from the port node to all of the LSUs that store to the port node.

Click on a node to select it and have the node attributes displayed in the Details pane.

Details
The Details pane shows the attributes of the node selected in the Kernel Memory Viewer pane. For example, when you select a memory in a kernel, the Details pane shows information such as the width and depths of the memory banks, as well as any user-defined attributes that you specified in your source code.

The content of the Details pane persists until you select a different node in the Kernel Memory Viewer pane.

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