Intel® FPGA SDK for OpenCL™ Standard Edition: Best Practices Guide

ID 683176
Date 9/24/2018
Public
Document Table of Contents

2.3. Reviewing Loop Information

The High Level Design Report ( <your_kernel_filename>/reports/report.html) file contains information about all the loops in your design and their unroll statuses. This loop analysis report helps you examine whether the is able to maximize the throughput of your kernel .

You can use the loop analysis report to help determine where to deploy one or more of the following pragmas on your loops:
  • #pragma unroll

    For details about #pragma unroll, see "Unrolling a Loop" in Intel FPGA SDK for OpenCL Standard Edition Programming Guide

  • #pragma loop_coalesce

    For details about #pragma loop_coalesce, see "Coalescing Nested Loops" in Intel FPGA SDK for OpenCL Standard Edition Programming Guide.

  • #pragma ii

    For details about #pragma ii, see "Specifying a loop initiation interval (II)" in Intel FPGA SDK for OpenCL Standard Edition Programming Guide.

  1. Click View reports > Loop Analysis .
  2. In the analysis pane, select Show fully unrolled loops to obtain information about the loops in your design.
  3. Consult the flowchart below to identify actions you can take to improve the throughput of your design.

    Remember: II refers to the initiation interval of a loop, which is the launch frequency of a new loop iteration. An II value of 1 is ideal; it indicates that the pipeline is functioning at maximum efficiency because the pipeline can process a new loop iteration every clock cycle.

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