Intel® FPGA SDK for OpenCL™ Standard Edition: Best Practices Guide

ID 683176
Date 9/24/2018
Public
Document Table of Contents

2.7.6. Area Report Messages for Private Variable Storage

The area report provides information on the implementation of private memory based on your OpenCL™ design. For single work-item kernels, the implements private memory differently, depending on the types of variable. The offline compiler implements scalars and small arrays in registers of various configurations (for example, plain registers, shift registers, and barrel shifter). The offline compiler implements larger arrays in block RAM.
Table 4.  Additional Information on Area Report Messages
Message Notes
Implementation of Private Memory Using On-Chip Block RAM
Private memory implemented in on-chip block RAM. The block RAM implementation creates a system that is similar to local memory for NDRange kernels.
Implementation of Private Memory Using On-Chip Block ROM
For each usage of an on-chip block ROM, the offline compiler creates another instance of the same ROM. There is no explicit annotation for private variables that the offline compiler implements in on-chip block ROM.
Implementation of Private Memory Using Registers
Implemented using registers of the following size:

- <X> registers of width <Y> and depth <Z> [(depth was increased by a factor of <N> due to a loop initiation interval of <M>.)]

- ...

Reports that the offline compiler implements a private variable in registers. The offline compiler might implement a private variable in many registers. This message provides a list of the registers with their specific widths and depths.
Implementation of Private Memory Using Shift Registers
Implemented as a shift register with <N> or fewer tap points. This is a very efficient storage type.

Implemented using registers of the following sizes:

- <X> register(s) of width <Y> and depth <Z>

- ...

Reports that the offline compiler implements a private variable in shift registers. This message provides a list of shift registers with their specific widths and depths.
The offline compiler might break a single array into several smaller shift registers depending on its tap points.
Note: The offline compiler might overestimate the number of tap points.
Implementation of Private Memory Using Barrel Shifters with Registers
Implemented as a barrel shifter with registers due to dynamic indexing. This is a high overhead storage type. If possible, change to compile-time known indexing. The area cost of accessing this variable is shown on the lines where the accesses occur.

Implemented using registers of the following size:

- <X> registers of width <Y> and depth <Z> [(depth was increased by a factor of <N> due to a loop initiation interval of <M>.)]

- ...

Reports that the offline compiler implements a private variable in a barrel shifter with registers because of dynamic indexing.

This row in the report does not specify the full area usage of the private variable. The report shows additional area usage information on the lines where the variable is accessed.

Note:
  • The area report annotates memory information on the line of code that declares or uses private memory, depending on its implementation.
  • When the offline compiler implements private memory in on-chip block RAM, the area report displays relevant local-memory-specific messages to private memory systems.

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