Intel® FPGA SDK for OpenCL™ Standard Edition: Best Practices Guide

ID 683176
Date 9/24/2018
Public
Document Table of Contents

2.8.2. Global Memory Interconnect

The ability to maximize memory bandwidth for read and write accesses is crucial for high performance computing. There are various types of global memory interconnect that can exist in an OpenCL™ system. A memory interconnect is sometimes referred to as a load-store unit (LSU).

Unlike a GPU, an FPGA can build any custom LSU that is most optimal for your application. As a result, your ability to write OpenCL code that selects the ideal LSU types for your application might help improve the performance of your design significantly.

When reviewing the HTML area report of your design, the values in the Global interconnect entry at the system level represents the size of the global memory interconnect.

Figure 35. HTML Area Report Showing the Size of the Global Memory Interconnect in an OpenCL Design

In the HTML report, the memory system viewer depicts global memory interconnects as loads (LD), stores (ST), and connections (gray lines).

Figure 36. System Viewer Result of Global Memory Interconnects in an OpenCL Design

The Intel® FPGA SDK for OpenCL Offline Compiler selects the appropriate type of LSU for your OpenCL system based on the memory access pattern of your design. Example LSU types include contiguous access (or consecutive access) and burst-interleaved access. Contiguous Memory Accesses and Optimize Global Memory Accesses illustrate the difference in access patterns between contiguous and burst-interleaved memory accesses, respectively.

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