Intel® FPGA SDK for OpenCL™ Standard Edition: Best Practices Guide

ID 683176
Date 9/24/2018
Document Table of Contents Tool Tip Options

To obtain additional information about the kernel source code, hover your mouse over channel accesses in the code to activate the tool tip.
Figure 65. The GUI: Source Code Tab Tool Tip
Attention: If your kernel undergoes memory optimization that consolidates hardware resources that implement multiple memory operations, statistical data might not be available for each memory operation. One set of statistical data will map to the point of consolidation in hardware.
Table 10.  Types of Information that a Source Code Tab Tool Tip Might Provide
Column Tool Tip Description Example Message Access Type
Attributes Cache Hits The number of memory accesses using the cache.

A high cache hit rate reduces memory bandwidth utilization.

Cache Hit%=30% Global memory
Unaligned Access The percentage of unaligned memory accesses.

A high unaligned access percentage signifies inefficient memory accesses. Consider modifying the access patterns in the kernel code to improve efficiency.

Unaligned Access%=20% Global memory
Statically Coalesced Indication of whether the load or store memory operation is statically coalesced.

Generally, static memory coalescing merges multiple memory accesses that access consecutive memory addresses into a single wide access.

Coalesced Global or local memory
Occupancy% Activity The percentage of time a predicated channel or memory instruction is enabled (that is, when conditional execution is true).
Note: The activity percentage might be less than the occupancy of the instruction.
Activity=20% Global or local memory, and channels
Bandwidth Burst Size The average burst size of the memory operation.

If the memory system does not support burst mode (for example, on-chip RAM), no burst information will be available.

Average Burst Size=7.6

(Max Burst=16)

Global memory