Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Document Table of Contents

4.1.20. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB


According to the Arm* architecture, any change in the Authentication Status register should be made visible to the processor after an exception entry or return, or an ISB. Although this is correctly achieved for all debug-related features, the ISB is not sufficient to make the changes visible to the trace flow. As a consequence, the WPTTRACEPROHIBITEDn signal(s) remain stuck to their old value up to the next exception entry or return, or to the next serial branch, even when an ISB executes.

A serial branch is one of the following:

  • Data processing to PC with the S bit set (for example, MOVS pc, r14)
  • LDM pc ^


Because of this erratum, the trace flow might not start or stop as expected by the program.


To work around this erratum, the ISB must be replaced by one of the events causing the change to be visible. In particular, replacing the ISB by a MOVS PC to the next instruction achieves the correct functionality.


Category 3