Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

4.1.19. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF

Description

CP14 read accesses to the Device Power-down and Reset Status (DBGPRSR) and Device Powerdown and Reset Control (DBGPRCR) registers generate an unexpected UNDEFINED exception when the DBGSWENABLE bit, bit[31] in the Coresight Components APB-AP Control/Status Word (CSW) register at offset 0x00, is 0, even when the CP14 accesses are performed from a privileged mode.

Impact

Because of this erratum, the Device Power-down and Reset Status (DBGPRSR) and the Device Powerdown and Reset Control (DBGPRCR) registers are not accessible when DBGSWENABLE=0.

This erratum is unlikely to cause any significant issue in Cortex* -A9 based systems because these accesses are mainly intended to be used as part of debug over power-down sequences, and the Cortex* -A9 does not support this feature.

Workaround

The workaround for this erratum is to temporarily set the DBGSWENABLE bit to 1 so that the DBGPRSR and DBGPRCR registers can be accessed as expected. There is no other workaround for this erratum.

Category

Category 3

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