Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

3.6. HPS SDRAM ECC Logging Problems

Description

While the HPS SDRAM ECC operates correctly, there can be minor issues logging the error address in the ecc_hmc_ocp_slv_block register block. Address logging errors can occur in the following situations:

  • During a read burst, if the HPS SDRAM controller is configured to interrupt on all errors (INTMODE.INTONCMP = 0) and if a single-bit error (SBE) occurs during an odd beat of a burst, the SERRADDRA register does not correctly store the address of the errant transaction.
  • During a read burst, if a double-bit error (DBE) occurs during an odd beat of a burst, the DERRADDRA register does not correctly store the address of the errant transaction.
  • During a read or write access, if the external parity error signal is asserted, the DERRADDRA register is erroneously updated.

Workaround

  • For systems executing read bursts where the frequency of single-bit errors is low, you can use interrupt-on-compare match mode to ensure the correct SBE address capture in the SERRADDRA register. To use this mode, set the compare value to 1 by setting the following register fields:

    • INTMODE.INTONCMP = 1
    • SERRCNTREG.SERRCNT = 1
  • There is no workaround to correctly store the errant address in the DERRADDRA register for double-bit errors that occur on the odd beat of a read burst.
  • There is no workaround to prevent the DERRADDRA register from being erroneously updated during a read or write access when the external parity error signal is asserted.

Status

Affects: All Arria 10 SX devices

Status: No fix planned

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