Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Document Table of Contents

3.8. Rarely, Bus or Bridge Hangs When Configuring or Using HPS SDRAM


Under very rare circumstances, an HPS bus or bridge can hang when performing an action involving SDRAM.

The L3 SDRAM interconnect uses an input clock generated by the I/O PLL in FPGA I/O Bank 2K. Immediately after FPGA I/O configuration, while the PLL is settling, the input clock is subject to high frequency transients. The L3 SDRAM interconnect is susceptible to timing violations resulting from these transients. These timing violations can infrequently result in corruption at random locations in the interconnect logic. Symptoms can include:

  • HPS bus hangs when accessing L3 SDRAM interconnect registers
  • HPS bus hangs when accessing HPS SDRAM
  • FPGA master transactions fail to complete when accessing HPS SDRAM through FPGA-to-SDRAM bridge


The issue can be avoided if the bootloader follows these guidelines:

  • Always warm reset the HPS after the FPGA I/O is configured
  • Access the SDRAM and the SDRAM interconnect only after the warm reset.

Intel® recommends that you use the SoC EDS v. 17.0, which implements the workaround for both the U-Boot and UEFI bootloaders.

If you need to implement the workaround in a custom bootloader, follow the software guidelines below.

  • Your bootloader will implement a warm reset before allowing any access to the SDRAM or SDRAM controller.

    After the warm reset, the bootloader will execute again. Your code must avoid initiating another warm reset after the first one, or you will create an infinite loop.

    You can use the isw_handoff7 register in the System Manager to keep track of whether the bootloader has previously initiated a warm reset. Prior to the warm reset, store a "magic number" (such as 0xDEADBEEF) in the isw_handoff7 register. This 32-bit register is otherwise unused, and preserved on HPS warm resets.

    Check this register on entry to the bootloader to determine if a warm reset is required. If it is set to the "magic number", clear it, and skip the warm reset, to avoid an infinite loop.

    Note: Your bootloader code should be re-entrant.
  • After the FPGA I/O is configured, and before initiating the warm reset, insert a delay of ( 1 ms + 65,536 × trefclk ), where trefclk is the reference clock period. This delay allows the I/O PLL to lock and the associated circuitry to settle.
  • Use the warm RAM boot feature, so that on the warm reset, the bootloader is re-entered without the BootROM trying to load again from flash. To use this feature, configure the System Manager warmram_* registers, as described in "Boot ROM Flow" and "Boot ROM Code" in the Intel® Intel® Arria® 10 Hard Processor System Technical Reference Manual.
  • Access the SDRAM and the SDRAM interconnect only after the warm reset.

During the HPS warm reset workaround loop, your system must not:

  • Reconfigure the FPGA I/O
  • Reset the HPS EMIF module


Affects: All Intel® Arria® 10 SX devices

Status: No device fix planned. Fixed in the SoC EDS v. 17.0. An SoC EDS patch is available for earlier versions.