Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

4. ARM Cortex-A9 MPCore and L2 Cache Errata

This section lists the ARM Cortex-A9 MPCore and L2 Cache errata. Each listed erratum has an associated category number which identifies the degree of the behavior.

The categories are as follows:

  • Category 1: Behavior has no workaround and severely restricts the use of the product in all, or the majority of applications, rendering the device unusable.
  • Category 2: Behavior contravenes the specified behavior and might limit or severely impair the intended use of the specified features, but does not render the product unusable in all or the majority of applications.
  • Category 3: Behavior that was not the originally intended behavior but should not cause any problems in applications.
Note: This device only contains category 2 and category 3 errata.
Table 2.  ARM Cortex-A9 MPCore Errata
Errata Listing Category Number

ARM Cortex-A9 MPU

761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain

Category 2

845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption

Category 2

740657: Global Timer Can Send Two Interrupts for the Same Event

Category 3

751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary

Category 3

754322: Faulty MMU Translations Following ASID Switch

Category 3

764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory

Category 3

794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation

Category 3

794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements

Category 3

794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue

Category 3

725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D

Category 3

729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface

Category 3

729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded

Category 3

751471: DBGPCSR Format Is Incorrect

Category 3

752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads

Category 3

754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store

Category 3

756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses

Category 3

757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP

Category 3

761321: MRC and MCR Are Not Counted in Event 0x68

Category 3

764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF

Category 3

771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB

Category 3

775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back

Category 3

ARM L2 Cache Controller

754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area

Category 3

765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23

Category 3

729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions

Category 3

ARM CoreSight Program Trace Macrocell (PTM)

720107: Periodic Synchronization Can Be Delayed and Cause Overflow

Category 3

711668: Configuration Extension Register Has Wrong Value Status

Category 3

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