Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

4.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain

Description

The Arm* architecture and the general rules of coherency require reads to the same memory location to be observed in sequential order. Because of some internal replay path mechanisms, the Cortex* -A9 can see one read access bypassed by a following read access to the same memory location, thus not observing the values in program order.

Impact

This erratum:
  • Applies only to devices with a dual Cortex* -A9 MPCore* configuration.
  • Can occur only on a process working in SMP mode on memory regions marked as normal memory write-back shared.
  • Can cause data coherency failure.

Workaround

The majority of multi-processing code examples follow styles that do not expose this erratum. Therefore, this erratum occurs rarely and is likely to affect only very specific areas of code that rely on a read-ordering behavior. There are two possible workarounds for this erratum:
  • Use LDREX instead of standard LDR in volatile memory places that require a strict read-ordering.
  • The alternative workaround is the recommended workaround for tool chain integration. This method requires insertion of a DMB between the affected LDR that requires this strict ordering rule.

For more information about integrating the workaround inside tool chains, please refer to the Programmer Advance Notice related to this erratum, ARM UAN 0004A.

Category

Category 2

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