Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations

Document Version Changes
2022.08.03 Added a new erratum: GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation.
2020.01.10 Added a new erratum: Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR).
2018.10.17 Added Knowledge Database reference to SD Card Image Partitioning in the Intel® Arria® 10 Design Recommendations section.
2018.09.11
  • Removed GX/GT references from Intel® Arria® 10 Design Recommendations section and subsections.
  • Added note regarding third-party IP errata in the Intel® Arria® 10 SX Device Errata and Design Recommendations section.
2017.11.06 Added: High VCCBAT Current when VCC is Powered Down
2017.07.28
  • Added a new section: Intel® Arria® 10 Design Recommendations.
  • Added a new erratum: Automatic Lane Polarity Inversion for PCIe Hard IP.
2017.07.17 Added the following errata:
  • Rarely, Bus or Bridge Hangs When Configuring or Using HPS SDRAM.
  • Hard Memory Controller Fails to Exit Self-Refresh Mode.
2016-07-15 Added a new erratum:HPS-to-FPGA Bridges Must Operate at 100 MHz or Above When Using the NoC Timeout Feature.
2016.06.10 Initial release

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