3.7. HPS-to-FPGA Bridges Must Operate at 100 MHz or Above When Using the NoC Timeout Feature
Intel recommends that all transactions on the HPS-to-FPGA and lightweight HPS-to-FPGA bridges be completed before shutting down and resetting the bridges. If the system is unable to meet this recommendation, the Arria 10 SoC device has a built-in timeout that can be enabled to force all outstanding transactions on the bridge to complete. If the HPS-to-FPGA and lightweight HPS-to-FPGA bridges are operating below 100 MHz, the timeout does not occur.
Ensure that the HPS-to-FPGA and lightweight HPS-to-FPGA bridges operate at 100 MHz or faster when the NoC timeout is enabled. The NoC timeout is enabled by setting the en bit in the System Manager’s noc_timeout register.
Affects: All Arria 10 SX devices
Status: No fix planned
Did you find the information on this page useful?