3.2. HPS Shared I/Os Inaccessible If FPGA Configuration Fails
If FPGA configuration fails, HPS shared and SDRAM I/Os are placed in an input tristate mode. If the HPS initiates FPGA configuration after an early I/O release, and configuration fails, any HPS access to a shared I/O peripheral or HPS SDRAM fails because of the tristated I/Os.
HPS dedicated I/Os are not affected.
This issue has no impact on full FPGA configuration using a Raw Binary File (.rbf) that contains both the FPGA core and peripheral configuration. In this case, the HPS can access HPS shared I/Os and HPS SDRAM only after the device has been successfully configured.
Provide a configuration failure avoidance or recovery mechanism that does not rely on access to HPS shared I/Os or HPS SDRAM. Intel recommends the following workarounds:
- If software executes from SDRAM, you can avoid this issue by checking the FPGA configuration code integrity in software before initiating configuration, loading the FPGA core configuration file in SDRAM and performing an integrity check before configuring the FPGA fabric. For example, the .rbf can have a cyclic redundancy check (CRC), which software can validate before programming the file contents into the FPGA core.
Intel also recommends enabling ECC to avoid correctable bitstream corruption issues.
- If software executes entirely from on-chip RAM, and a configuration failure occurs, software can recover by reprogramming the peripheral configuration .rbf to reactivate the HPS shared and SDRAM I/Os. After the I/Os have been reconfigured, software can reconfigure the FPGA fabric, either with the same image or with a fallback image (to prevent the same failure from recurring).
Affects: All Arria 10 SX devices
Status: No fix planned
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