Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

3.1. Faster Boot Frequency Requires Higher Operating VCCL_HPS Supply

Description

The Arria 10 SoC device supports both a default and a faster boot clock mode. To use faster boot clock frequencies, you can change the CSEL fuses from their default setting of 0x0 to any value between 0x7 to 0xE. These settings allow boot ROM code to configure the HPS PLL to run at faster frequencies, depending on the value of the external oscillator. Refer to the "CSEL Encodings for hps_clk_f = 0" table in the SoC Security chapter of the Arria 10 Technical Reference Manual.

The faster boot clock frequencies require the VCCL_HPS voltage to be at least 0.95V, to prevent boot failure or system instability.

However, if you leave the CSEL fuses at their default boot mode setting of 0x0, the VCCL_HPS voltage can be 0.9V.

Workaround

None

Status

Affects: All Intel® Arria® 10 SX devices

Status: No planned fix

Did you find the information on this page useful?

Characters remaining:

Feedback Message