Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

3.4. HPS EMIF Write Performance Degradation When Using ECC and a 16-bit Interface

Description

When you configure the HPS external memory interface (EMIF) to be 16 bits wide with error checking and correction (ECC) enabled, the ECC will sometimes perform unnecessary read-modify-write (RMW) cycles, resulting in degraded write performance. No data corruption occurs.

Workaround

Disable the RMW feature in the EMIF by clearing the RMW_EN bit in the ECCCTRL2 register (0xFFCFB104).

Note: If you disable this feature, you must observe the following constraints:
  • You must also disable the EMIF ECC auto-correction, because this feature requires RMW to be enabled. This feature is disabled by writing a 0 to the AUTOWB_EN bit in the ECCCTRL2 register.
  • Partial writes are not supported. All writes must be 16-bit aligned and contain a multiple of 2 bytes. For example, a 16-bit write or 32-bit write is allowed, but a single byte write is not.

Status

Affects: All Intel® Arria® 10 SX devices

Status: No fix planned

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