Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Document Table of Contents

4.1.17. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP


The Arm* Architecture specifies that Arm* opcodes of the form 11110 100x001 xxxx xxxx xxxx xxxx xxxx are “unallocated memory hint (treat as NOP)” if the core supports the MP extensions, as the Cortex* -A9 does.

Because of this erratum, the Cortex* -A9 generates an UNDEFINED exception when bits [15:12] of the instruction encoding are different from 4'b1111, instead of treating the instruction as a NOP.


Because of this erratum, an unexpected UNDEFINED exception might be generated. In practice, this erratum is unlikely to cause any significant issue because such instruction encodings are not supposed to be generated by any compiler, nor used by any handcrafted program.


The workaround for this erratum is to modify the instruction encoding with bits[15:12]=4'b1111, so that the Cortex* -A9 treats the instruction properly as a NOP.

If it is not possible to modify the instruction encoding as described, the UNDEFINED exception handler has to cope with this case and emulate the expected behavior of the instruction, that is, it must do nothing (NOP), before returning to normal program execution.


Category 3