ID 683161
Date 8/03/2022
Public

## 4.1.2. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption

### Description

Under very rare timing circumstances, data corruption might occur on a dirty cache line that is evicted from the L1 data cache due to another cache line being entirely written.

The erratum requires the following conditions:

• The CPU contains a dirty line in its data cache.
• The CPU performs at least four full cache line writes, one of which is causing the eviction of the dirty line.
• The other CPU, or the ACP, is performing a read or write operation on the dirty line.

The issue requires very rare timing conditions to reach the point of failure. These timing conditions depend on the CPU micro-architecture, and are not controllable in software:

• The CPU must be in a transitional mode that might be triggered by the detection of the first two full cache line writes.
• The evicted line must remain stalled in the eviction buffer, which is likely to be caused by congested write traffic.
• The other coherent agent, either the other CPU or the ACP, must perform its coherency request on the evicted line while it is in the eviction buffer.

### Impact

This erratum might lead to data corruption.

### Workaround

A workaround for this erratum is provided by setting bit[22] of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1. The bit can be written in secure state only, with the following read-modify-write code sequence:

MRC p15,0,rt,c15,c0,1
ORR rt,rt,#0x00400000
MCR p15,0,rt,c15,c0,1 

When this bit is set, the processor is unable to switch into read-allocate (streaming) mode, which means this erratum cannot occur.

Setting this bit could possibly result in a visible drop in performance for routines that perform intensive memory accesses, such as memset() or memcpy(). However, the workaround is not expected to create any significant performance degradation in most standard applications.

Category 2