3.9. Hard Memory Controller Fails to Exit Self-Refresh Mode
The hard memory controller does not respond to a self-refresh exit command issued through memory-mapped registers. If your system attempts to take the controller out of self-refresh mode by this method, the controller is likely to lock up.
You can work around this issue by temporarily placing the hard memory controller in self-refresh auto exit mode, as follows:
- Before placing the SDRAM in the self-refresh state, make sure the memory controller is idle. Verify that it has completed all read and write accesses, and that all other buses mastering the controller are idle.
- With the memory controller idle, write 0 to bit 5 of the Memory-Mapped Sideband Config 2 register (sbcfg2) to disable self-refresh auto exit.
- Write 0xF to the Memory-Mapped Self Refresh Request register (Sideband4) to place the SDRAM in self-refresh mode.
- Poll the Memory-Mapped Self Refresh Ack register (Sideband9) until its value is 1, confirming the SDRAM has entered self-refresh mode.
- To exit self-refresh mode, write 1 to bit 5 of the Memory-Mapped Sideband Config 2 register (sbcfg2), to enable self-refresh auto exit.
- Write 0 to the Memory-Mapped Self Refresh Request register to de-assert the self-refresh request.
- To exit self-refresh mode, send an arbitrary read or write command to the memory controller.
- Poll the Memory-Mapped Self Refresh Ack register until its value is 0, confirming the SDRAM has exitted self-refresh mode.
- Write 0 to bit 5 of the Memory-Mapped Sideband Config 2 register to disable self-refresh auto exit.
Affects: All Arria 10 devices
Status: No device fix planned.
Did you find the information on this page useful?