Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

4.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23

Description

When the prefetch feature is enabled (bits[29:28] of the Auxiliary or Prefetch Control register set HIGH), the prefetch offset bits of the Prefetch Control Register (bits[4:0]) configure the advance taken by the prefetcher compared to the current cache line. Refer to the PL310 Cache Controller Technical Reference Manual for more information. One requirement for the prefetcher is to not go beyond a 4KB boundary. If the prefetch offset is set to 23 (5’b10111), this requirement is not fulfilled and the prefetcher can cross a 4 KB boundary.

This problem occurs when the following conditions are met:

  • One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or Prefetch Control Register) is set HIGH.
  • The prefetch offset bits are programmed with value 23 (5’b10111).

Impact

When the conditions above are met, the prefetcher can issue linefills beyond a 4 KB boundary compared to the original transaction. System issues can result because those linefills can target a new 4 KB page of memory space, regardless of the page attribute settings in the L1 MMU.

Workaround

A workaround for this erratum is to program the prefetch offset with any value except 23.

Category

Category 3

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