Intel® Arria® 10 SX Device Errata and Design Recommendations

ID 683161
Date 8/03/2022
Public
Document Table of Contents

4.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions

Description

The "High Priority for SO and Dev reads" feature can be enabled by setting bit[10] of the PL310 Auxiliary Control Register. When enabled, this feature gives priority to strongly ordered and device reads over cacheable reads in the PL310 AXI master interfaces. When PL310 receives a continuous flow of strongly ordered or device reads, this configuration can prevent cacheable reads that miss in the L2 cache from being issued to the L3 memory system.

This erratum occurs when the following conditions are met:

  • Bit[10] "High Priority for SO and Dev reads enable" of the PL310 Auxiliary Control Register is set to 1.
  • PL310 receives a cacheable read that misses in the L2 cache.
  • PL310 receives a continuous flow of strongly ordered or device reads that take all address slots in the master interface.

Impact

When the conditions above are met, the linefill resulting from the L2 cache miss is not issued until the flow of SO/Device reads stops. Note that each PL310 master interface has four address slots, so that the Quality of Service issue only appears on the cacheable read if the L1 is able to issue at least four outstanding SO/Device reads.

Workaround

A workaround is only necessary in systems that are able to issue a continuous flow of strongly ordered or device reads. In such a case, the workaround is to disable the "High Priority for SO and Dev reads" feature, which is the default behavior.

Category

Category 3

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