Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 12/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4. SEU Sensitivity Processing

Reconfiguring a running FPGA has a significant impact on the system using the FPGA. Using SEU sensitivity processing, you can identify if the SEU on a CRAM bit is critical to the function of your FPGA design. You can perform SEU sensitivity processing using the Advanced SEU Detection IP core.

In many instances, an SEU impacts CRAM bits that are not critical to the function of the design. For example:

  • Configuration bits that are not used because they control unused logic and routing wires
  • Portions such as test circuitry that are not utilized in the functional operations of the FPGA
  • Non-critical functions that may be logged but do not need to be reprogrammed or reset

When planning recovery from an SEU, you must account for the time required to bring the FPGA to a state consistent with the current state of the system. For example, if an internal state machine is in an illegal state, it may require reset. In addition, the surrounding logic may need to account for this unexpected operation.

Typically, only 40% of all CRAM bits can be used even in the most heavily utilized device. This means that only 40% of SEUs require intervention and you can ignore the rest.