Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

1.1. SEU Mitigation Techniques

The Intel® Quartus® Prime software offers several features to detect, correct, and characterize the effects of SEU on your designs. Additionally, Intel® Agilex™ FPGAs contain dedicated circuitry to help detect and correct errors.

Intel® Agilex™ SEU mitigation features can benefit the system by:

  • Ensuring the system functions properly at all time
  • Preventing a system malfunction caused by an SEU event
  • Handling the SEU event if it is critical to the system
Table 1.  SEU Mitigation Areas and Approaches for Intel® Agilex™ Devices
Area SEU Mitigation Approach
Error detection and correction Enable the error detection and correction (EDC) feature to detect CRAM SEU events and automatically correct the CRAM contents.
Memory block error correction code Take advantage of the error correction code (ECC) feature and the special layout design of the Intel® Agilex™ M20K memory blocks to reduce SEU failures in time (FIT) rate to almost zero.
SEU sensitivity processing Use the sensitivity processing feature to identify if the SEU on a CRAM bit location is critical to the function of your compiled FPGA design bitstream file.
Fault injection

Use the fault injection feature to help you validate system response to the SEU event by intentionally changing the CRAM state to trigger an error.

Intel® Agilex™ supports ECC error injection to M20K blocks.

Hierarchy tagging Use hierarchy tagging, together with sensitivity processing and fault injection, to report SEU and constrain error injection to specific portions of your design logic.
Triple modular redundancy Use triple modular redundancy (TMR) technique on critical logic such as state machines to improve hardware fault tolerance.

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