Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings

Table 9.   Advanced SEU Detection IP Core Parameter Settings
Parameters Value Default Value Description
Use on-chip sensitivity processing
  • On
  • Off
On Select to use external memory interface to access sensitivity data and perform SEU location look-up by the IP.
Largest ASD region ID used 1 to 32 1

Specifies the largest ASD region ID used in the design.

This option is available if you turn on Use on-chip sensitivity processing.

The maximum number of region IDs classifications you can use in a design is 163.

Sensitivity data start address 0x0 0x0

Specifies a constant offset to add to all addresses generated by the external memory interface.

This option is available if you turn on Use on-chip sensitivity processing.

Show raw SEU error message
  • On
  • Off
Off

Select to show raw SEU error message.

This option is available if you turn on Use on-chip sensitivity processing.

SEU error fifo depth
  • 2
  • 4
  • 8
  • 16
  • 32
  • 64
4

Specifies the number of SEU errors to store.

Use with Fault Injection Debugger Tool
  • On
  • Off
Off

Turn on to use the IP with the Fault Injection Debugger tool.

3 Number of region ID in-use is limited by the region mask specified in the .smh.

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