1. Intel® Agilex™ SEU Mitigation Overview 2. Intel® Agilex™ CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel® Agilex™ SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel® Agilex™ SEU Mitigation User Guide Archives 7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
2.5. Design Hierarchy Sensitivity Classification
To classify the criticality of each logic block, generate design partitions and assign them sensitivity ID tags in the Intel® Quartus® Prime software. The software stores these classifications in the .smh file. When an operation error occurs, the system can refer to the file to determine the error's criticality and take appropriate actions.
The Intel® Quartus® Prime software generates the sensitivity mask for the entire design. The .smh file contains a mask for the design's sensitive bits in a compressed format.
- To generate .smh files, you need a licensed version of the Intel® Quartus® Prime software.
- To access the .smh file, add an instance of the Advanced SEU Detection Intel® FPGA IP to your design.