Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

1.3. Memory Blocks

Intel® Agilex™ devices contain three types of memory blocks: Embedded SRAM (eSRAM) blocks, M20K blocks, and memory logic array blocks (MLABs). The M20K blocks and eSRAM blocks support ECC. The ECC feature detects and corrects data errors at the output of the memory.
Note: When you engage the ECC feature, you cannot use the byte enable and coherent read features.
Table 2.  ECC for M20K and eSRAM Blocks
Item M20K Block eSRAM Block
Built-in support In ×32-wide simple dual-port mode In ×64-wide simple dual-port mode.
Features

32-bit word error detection and correction:

  • Single-error correction
  • Double-adjacent-error correction
  • Triple-adjacent-error correction

The ECC cannot guarantee detection or correction of non-adjacent two-bit (or more) errors.

64-bit word error detection or correction:

  • Single-error correction
  • Double-error detection
Flags indicating memory status
  • e—error
  • ue—uncorrectable error

The status flags are part of the regular outputs from the memory block.

  • c{7:0}_error_correct_0—error corrected
  • c{7:0}_error_detect_0—error detected

When you engage ECC, the M20K memory runs slower than in non-ECC simple dual-port mode. To achieve a higher performance—compared to non-pipeline ECC mode—at the expense of a one-cycle latency, enable the optional ECC pipeline registers before the output decoder.

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