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2.1. CRAM Error Detection and Correction
|Single bit error||Yes||Yes|
|Double adjacent errors||Yes||Yes|
|Multiple bits error||Yes||—|
The following figure shows the EDC operation. For a given Intel® Agilex™ device, the total sectors are divided equally into groups. The number of sectors per group are based on Smax, which is the maximum number of sectors allowed to run the EDC operation concurrently in a same thread. The Smax has device dependency. You can get the Smax details in the System Window: the number of thread(s). In this case, Smax = 5, each group runs at a different thread during SEU detection and correction. The first group will run the EDC process at time T0. This is followed by the second and third group at time T1 and T2 respectively, until the last available group. The time duration to complete one cycle of the EDC process for all the groups is the minimum SEU interval of the device.
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