1. Intel® Agilex™ SEU Mitigation Overview 2. Intel® Agilex™ CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel® Agilex™ SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel® Agilex™ SEU Mitigation User Guide Archives 7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
2.3.1. Advanced SEU Detection Intel® FPGA IP
The Advanced SEU Detection Intel® FPGA IP allows you to perform runtime on-chip and off-chip lookup sensitivity processing for SEU errors.
- On-chip—the sensitivity processing soft IP provides error location reporting and lookup.
- Off-chip—an external unit such as a microprocessor performs error location lookup using information from the error message queue.
The Advanced SEU Detection IP does the following:
- Communicates with the secure device manager (SDM) to detect SEU event by sending commands and receiving responses for SEU error reports.
- Read sensitivity map header (.smh) file to allow on-chip or off-chip lookup sensitivity processing, and report criticality of SEU error occurrence in device based on the specified regions in the file.
Note: You cannot simulate the Advanced SEU Detection IP because the IP receives the response from SDM. To validate this IP core, Intel recommends that you perform hardware evaluation.
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