Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

2.1. Error Message Queue

When it detects an SEU error, the Intel® Agilex™ device stores the error information in the error message queue. Each error message records the sector address, type, and location of the error. The error message queue is capable of storing a maximum of eight different messages. A warning message appears if the error message queue has more than eight different messages. Click Read EMR to display and clear the error message queue.

The SEU_ERROR signal goes high whenever the error message queue contains one or more error messages. The signal stays high if there is an error message in the queue. The SEU_ERROR signal goes low only when the SEU error message queue is empty—after you read out all the error messages. You must set the SEU_ERROR pin function to observe the SEU_ERROR pin behavior.

To retrieve the error message queue contents, use these tools:

  • Intel® Quartus® Prime Fault Injection Debugger
  • Advanced SEU Detection Intel® FPGA IP
Table 4.  Error Message Queue Bit Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in avst_seu_source_data signal)

32 31:24 Reserved
23:16 Sector address of the error
15:4 Reserved
3:0 Number of errors detected in the sector minus one

Error location1

(Least significant 32-bit word in avst_seu_source_data signal)

32 31:29 Error type:
  • 001—single bit error
  • 010—double adjacent bit error
  • 011—uncorrectable multiple bits error
28 Correction Status:
  • 0—not corrected
  • 1—corrected
27:24 Reserved
23:12 Bit position within the frame
11:0 Combination of row and frame index
1 For single bit error with internal scrubbing, the error location provides the error bit position. For multiple bit errors or single bit error without internal scrubbing, bit [23:0] returns 0.

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