Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

1.2. Configuration RAM

FPGAs use memory in user logic (bulk memory and registers) and in configuration RAM (CRAM). The Intel® Quartus® Prime Programmer loads the CRAM with your design (.sof file). During device configuration, the CRAM configures all FPGA logic and routing.

If an SEU strikes a CRAM bit that is not in use, the effect can be harmless. However, if the affected CRAM bit is in use for critical internal signal routing or lookup table logic bits, the device may experience a functional error.

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