1. Intel® Agilex™ SEU Mitigation Overview 2. Intel® Agilex™ CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel® Agilex™ SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel® Agilex™ SEU Mitigation User Guide Archives 7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
1.2. Configuration RAM
FPGAs use memory in user logic (bulk memory and registers) and in configuration RAM (CRAM). The Intel® Quartus® Prime Programmer loads the CRAM with your design (.sof file). During device configuration, the CRAM configures all FPGA logic and routing.
If an SEU strikes a CRAM bit that is not in use, the effect can be harmless. However, if the affected CRAM bit is in use for critical internal signal routing or lookup table logic bits, the device may experience a functional error.