Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

5.1.2. Advanced SEU Detection IP Core Ports

Figure 13.  Advanced SEU Detection IP Core On-Chip Sensitivity Processing Block Diagram


Table 10.   Advanced SEU Detection IP Core On-Chip Sensitivity Processing Ports
Ports Width Direction Description
clk 1 Input User input clock. The maximum frequency is 250 MHz.
reset 1 Input Active high, synchronous reset signal.
Note: For IP core instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
sys_error 1 Output Logic high indicates that there is an error in the system while retrieving the SEU error.
busy 1 Output Logic high indicates that the Advanced SEU Detection IP core is busy processing the SEU data. The signal goes low when processing completes with assertion of the critical_error or noncritical_error signal.
generic_sdm_valid_out 1 Output Logic high for one clock cycle indicates that the device detects an SDM ECC or SmartVID error.
generic_sdm_data_out 64 Output Outputs the SDM ECC or SmartVID error message content.
critical_clear 1 Input Assert high to clear the error report (critical_error, noncritical_error, regions_report, and seu_data) for the last processed SEU data input.
critical_error 1 Output Logic high indicates that a.smh lookup determined that the SEU error is in a critical region.
noncritical_error 1 Output Logic high indicates that a .smh lookup determined that the SEU error is in a non-critical region.
seu_data 64 Output Shows the SEU error message for the last processed SEU data input. The port is available if you turn on Show raw SEU error message. For more information, refer to the related information about the error message queue.
regions_report 1–32 Output Indicates the region ID for the error as reported by the .smh lookup. The port width of this signal is set by the Largest ASD region ID used parameter.
address 32 Output Avalon® memory-mapped interface address bus in unit of Byte addressing.
read 1 Output Avalon® memory-mapped interface read control signal.
waitrequest 1 Input Avalon® memory-mapped interface wait request signal.
readdata 32 Input Avalon® memory-mapped interface data bus.
readdatavalid 1 Input Avalon® memory-mapped interface data valid signal.
Figure 14.  Advanced SEU Detection IP Core Off-Chip Sensitivity Processing Block Diagram


Table 11.   Advanced SEU Detection IP Core Off-Chip Sensitivity Processing Ports
Ports Width Direction Description
clk 1 Input User input clock. The maximum frequency is 250 MHz.
reset 1 Input Active high, synchronous reset signal.
Note: For IP core instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
sys_error 1 Output Logic high indicates that there is an error in the system while retrieving the SEU error.
generic_sdm_valid_out 1 Output Logic high for one clock cycle indicates that the device detects an SDM ECC or SmartVID error.
generic_sdm_data_out 64 Output Outputs the SDM ECC or SmartVID error message content.
data 64 Output Avalon® streaming interface data signal that provides SEU error message from the FIFO entry.
valid 1 Output Avalon® streaming interface data valid signal that indicates the avst_seu_source_data signal contains valid data.
ready 1 Input Avalon® streaming interface ready signal.

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