Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

2.4.1. Hierarchy Tagging

The Intel® Quartus® Prime hierarchy tagging feature allows you to improve your design's effective FIT rate by tagging only the logic that are critical to device operation.

You can define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides.

Other advantages of hierarchy tagging:

  • Increases system stability by avoiding disruptive recovery procedures for inconsequential errors
  • Allows diverse corrective actions for different design logic

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