Intel® Agilex™ SEU Mitigation User Guide

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ID 683128
Date 12/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ SEU Mitigation Overview 2. Intel® Agilex™ CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel® Agilex™ SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel® Agilex™ SEU Mitigation User Guide Archives 7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide
1. Intel® Agilex™ SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel® Agilex™ CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel® Agilex™ SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel® Agilex™ SEU Mitigation Overview
2. Intel® Agilex™ CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel® Agilex™ SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel® Agilex™ SEU Mitigation User Guide Archives
7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide

4.4. Assigning Regions for Hierarchy Tagging

To define the FPGA regions for tagging, assign an ASD region to the location. You can specify an ASD region value for any portion of your design hierarchy in the Design Partitions Window.
  1. From the Intel® Quartus® Prime menu, select Assignments > Design Partitions Window.
  2. If the ASD Region column is not visible in the Design Partitions Window, right-click anywhere in the header row and turn on ASD Region.
    Figure 9.  ASD Region Column in the Design Partitions Window
  3. Enter the logic sensitivity ID value from 0 to 32 for any partition to assign it to a specific ASD region.
    The logic sensitivity ID represents the sensitivity tag to associate with the partition:
    • A sensitivity tag of 1 means that there is no assignment and indicates a basic sensitivity level, which is "region used in design".
    • A sensitivity tag of 0 is reserved and indicates unused CRAM bits. You can explicitly set a partition to 0 to indicate that the partition is not critical. This setting excludes the partition from sensitivity mapping.
    Note: You can use the same sensitivity tag for multiple design partitions.
When you compile the design, the Intel® Quartus® Prime software generates sensitivity data as a standard Intel® hex (big endian) .smh file during the .sof file generation.
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