Intel® Agilex™ SEU Mitigation User Guide

ID 683128
Date 9/26/2022
Public
Document Table of Contents

4.4. Assigning Regions for Hierarchy Tagging

To define the FPGA regions for tagging, assign an ASD region to the location. You can specify an ASD region value for any portion of your design hierarchy in the Design Partitions Window.
  1. From the Intel® Quartus® Prime menu, select Assignments > Design Partitions Window.
  2. If the ASD Region column is not visible in the Design Partitions Window, right-click anywhere in the header row and turn on ASD Region.
    Figure 6.  ASD Region Column in the Design Partitions Window
  3. Enter the logic sensitivity ID value from 0 to 32 for any partition to assign it to a specific ASD region.
    The logic sensitivity ID represents the sensitivity tag to associate with the partition:
    • A sensitivity tag of 1 means that there is no assignment and indicates a basic sensitivity level, which is "region used in design".
    • A sensitivity tag of 0 is reserved and indicates unused CRAM bits. You can explicitly set a partition to 0 to indicate that the partition is not critical. This setting excludes the partition from sensitivity mapping.
    Note: You can use the same sensitivity tag for multiple design partitions.
When you compile the design, the Intel® Quartus® Prime software generates sensitivity data as a standard Intel® hex (big endian) .smh file during the .sof file generation.

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