40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
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Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

3.3.1. Signals of MAC and PHY Variations Without Adapters

The signals of the MAC and PHY variations without adapters are described in the following formats:

  • The figure identifies the IP core interfaces and the presence or absence of various signals in MAC and PHY, PHY-only, and MAC-only IP core variations.
  • The tables identify the different signals available in TX-only, RX-only, and duplex IP core variations.
  • Links guide you to descriptions for the individual signals, by interface. The links are available only if you are viewing this topic in the context of the Functional Description chapter of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.
Figure 41. Top-Level Signals of the 40-100GbE IP Core Without Adapters

The following tables list the signals for the 40‑100GbE MAC and PHY IP core without adapters:

  • Transmit side signals configured only in TX-only and duplex IP core variations
  • Receive side signals configured only in RX-only and duplex IP core variations
  • Signals configured in TX-only, RX-only, and duplex IP core variations

For links to the relevant interface information, including a description of each signal, refer to the Related Links below.

Table 35.  40-100GbE MAC and PHY IP Core Without Adapters: Transmit Side Signals

Signal Name

Direction

Interface

mac_tx_arst_ST

Input

Resets

pcs_tx_arst_ST

Input

tx_serial [3:0] (40GbE and CAUI–4)

tx_serial [9:0] (standard 100GbE)

Output

Transceiver PHY serial data interface

tx_lanes_stable

Output

PHY status

clk_txmac

Input

Clocks

TX client interface without adapters (custom streaming interface)

din[<w>*64-1:0]

Input

TX client interface without adapters (custom streaming interface)

din_start[<w>-1:0]

Input

din_end_pos[<w>*8-1:0]

Input

din_ack

Output

pause_insert_tx

Input

Pause control and generation interface

The _to_tx signals are not visible in duplex variations.

pause_insert_time[15:0]

Input

pause_insert_mcast

Input

pause_insert_dst[47:0]

Input

pause_insert_src[47:0]

Input

pause_match_to_tx

Input

pause_time_to_tx[15:0]

Input

remote_fault_to_tx

Input

Link fault signaling interface

These two signals are not visible in duplex variations.

local_fault_to_tx

Input

tx_inc_64

Output

Statistics counter increment vectors

tx_inc_127

Output

tx_inc_255

Output

tx_inc_511

Output

tx_inc_1023

Output

tx_inc_1518

Output

tx_inc_max

Output

tx_inc_over

Output

tx_inc_mcast_data_err

Output

tx_inc_mcast_data_ok

Output

tx_inc_bcast_data_err

Output

tx_inc_bcast_data_ok

Output

tx_inc_ucast_data_err

Output

tx_inc_ucast_data_ok

Output

tx_inc_mcast_ctrl

Output

tx_inc_bcast_ctrl

Output

tx_inc_ucast_ctrl

Output

tx_inc_pause

Output

tx_inc_fcs_err

Output

tx_inc_fragment

Output

tx_inc_jabber

Output

tx_inc_sizeok_fcserr

Output

Table 36.  40-100GbE MAC and PHY IP Core Without Adapters: Receive Side Signals

Signal Name

Direction

Description

mac_rx_arst_ST

Input

Resets

pcs_rx_arst_ST

Input

rx_serial [3:0] (40GbE and CAUI–4)

rx_serial [9:0] (standard 100GbE)

Input

Transceiver PHY serial data interface

lanes_deskewed

Output

PHY status

clk_rxmac

Input

Clocks

RX client interface without adapters (custom streaming interface)

dout_d[<w>*64-1:0]

Output

RX client interface without adapters (custom streaming interface)

dout_c[<w>*8-1:0]

Output

dout_first_data[<w>-1:0]

Output

dout_last_data[<w>*8-1:0]

Output

dout_runt_last_data[<w>-1:0]

Output

dout_payload[<w>-1:0]

Output

dout_fcs_error

Output

dout_fcs_valid

Output

dout_dst_addr_match[<w>-1:0]

Output

dout_valid

Output

pause_match_from_rx

Output

Pause control and generation interface

These two signals are not visible in duplex variations.

pause_time_from_rx[15:0]

Output

remote_fault_from_rx

Output

Link fault signaling interface

These two signals are not visible in duplex variations.

local_fault_from_rx

Output

rx_inc_runt

Output

Statistics counter increment vectors

rx_inc_64

Output

rx_inc_127

Output

rx_inc_255

Output

rx_inc_511

Output

rx_inc_1023

Output

rx_inc_1518

Output

rx_inc_max

Output

rx_inc_over

Output

rx_inc_mcast_data_err

Output

rx_inc_mcast_data_ok

Output

rx_inc_bcast_data_err

Output

rx_inc_bcast_data_ok

Output

rx_inc_ucast_data_err

Output

rx_inc_ucast_data_ok

Output

rx_inc_mcast_ctrl

Output

rx_inc_bcast_ctrl

Output

rx_inc_ucast_ctrl

Output

rx_inc_pause

Output

rx_inc_fcs_err

Output

rx_inc_fragment

Output

rx_inc_jabber

Output

rx_inc_sizeok_fcserr

Output

Table 37.  40-100GbE MAC and PHY IP Core Without Adapters: Common Signals

Signal Name

Direction

Description

pma_arst_ST

Input

Resets

clk_ref

Input

Clocks

tx_clk_ref

Input

Clocks

In Sync–E variations, these two clock signals replace clk_ref. All Sync–E variations are duplex IP cores.

rx_clk_ref

Input

rx_recovered_clk

Output

Clocks

This signal is present only in Sync-E variations.

status_addr[15:0]

Input

Control and status interface

status_read

Input

status_write

Input

status_writedata[31:0]

Input

status_readdata[31:0]

Output

status_readdata_valid

Output

clk_status

Input

Clocks

remote_fault_status

Output

Link fault signaling interface

These two signals are available only in duplex variations.

local_fault_status

Output

reconfig_to_xcvr

Input

External reconfiguration controller interface

These signals are available in Arria V GZ and Stratix V devices only.

The _to_xcvr<n> and _from_xcvr<n> signals are present only in CAUI–4 variations.

reconfig_to_xcvr0

Input

reconfig_to_xcvr1

Input

reconfig_to_xcvr2

Input

reconfig_to_xcvr3

Input

reconfig_from_xcvr

Output

reconfig_from_xcvr0

Output

reconfig_from_xcvr1

Output

reconfig_from_xcvr2

Output

reconfig_from_xcvr3

Output

upi_mode_en[3:0]

Input

40GBASE-KR4 microprocessor interface. These signals are present only in 40GBASE-KR4 variations for which you turn on Enable microprocessor interface. All 40GBASE-KR4 variations are in Duplex mode.

upi_adj[7:0]

Input

upi_inc[3:0]

Input

upi_dec[3:0]

Input

upi_pre[3:0]

Input

upi_init[3:0]

Input

upi_st_bert[3:0]

Input

upi_train_err[3:0]

Input

upi_lock_err[3:0]

Input

upi_rx_trained[3:0]

Input

upo_enable[3:0]

Output

upo_frame_lock[3:0]

Output

upo_cm_done[3:0]

Output

upo_bert_done[3:0]

Output

upo_ber_cnt[4*<bcw>-1:0] (width varies with <bcw> = BER counter width)

Output

upo_ber_max[3:0]

Output

upo_coef_max[3:0]

Output

rc_busy[3:0]

Input

40GBASE-KR4 reconfiguration interface. These signals are present only in 40GBASE-KR4 variations for which you turn on Enable KR4 Reconfiguration. All 40GBASE-KR4 variations are in Duplex mode.

The lt_start_rc, main_rc, post_rc, pre_rc, and tap_to_upd signals are present only if you turn on Enable Link Training.

The dfe_start_rc, dfe_mode, ctle_start_rc, ctle_rc, and ctle_mode signals are present only if you turn on Enable RX equalization.

lt_start_rc[3:0]

Output

main_rc[23:0]

Output

post_rc[19:0]

Output

pre_rc[15:0]

Output

tap_to_upd[11:0]

Output

seq_start_rc[3:0]

Output

dfe_start_rc[3:0]

Output

dfe_mode[7:0]

Output

ctle_start_rc[3:0]

Output

ctle_rc[15:0]

Output

ctle_mode[7:0]

Output

pcs_mode_rc[5:0]

Output

en_lcl_rxeq[3:0]

Output

rxeq_done[3:0]

Input

reco_mif_done

Input

Related Information
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