40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.2.3.4. 40-100GbE IP Core CRC Checking

The 32-bit CRC field is received in the order: X32, X30, . . . X1, and X0 , where X32 is the most significant bit of the FCS field and occupies the least significant bit position in the first FCS byte.

If a CRC32 error is detected, the RX MAC marks the frame invalid by asserting the dout_fcs_error and dout_fcs_valid signals, as well as the l<n>_rx_error[1] (or rx_error[1]) signal.

When operating in the cut-through or store and forward mode, with Avalon–ST or the custom streaming client interface, the FCS result is always preserved.