40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.2.16. PCS Test Pattern Generation and Test Pattern Check

The PCS can generate a test pattern and detect a scrambled idle test pattern. PCS test-pattern mode is suitable for receiver tests and for certain transmitter tests.

When bit 0 of the TEST_MODE register at offset 0x019 has the value of 1, a scrambled idle pattern is enabled. In this mode, the scrambler generates a test pattern. The scrambler does not require seeding during test-pattern operation. The input to the scrambler is a control block (blocktype=0x1E). The TX PCS adds synchronous headers and alignment markers to the data stream, enabling the RX PCS to align and deskew the PCS lanes.

For information about the definition of idle test patterns, refer to Figure 82–5—64B/66B block formats illustrated in the IEEE 802.3ba 2010 100G Ethernet Standard.

Figure 39. PCS Test Pattern Generation

The scrambled idle test-pattern checker utilizes the block lock state diagram, the alignment marker state diagram, the PCS deskew state diagram, and the descrambler; these blocks operate as if in normal data reception. The bit error rate (BER) monitor state diagram is disabled during RX test-pattern mode. When align_status is true and the scrambled idle RX test-pattern mode is active, the scrambled idle test-pattern checker observes the synchronous header and the output from the descrambler. When the synchronous header and the output of the descrambler is an idle pattern, a match is detected. When operating in scrambled idle test pattern, the test-pattern error counter counts blocks with a mismatch. Any mismatch indicates an error and shall increment the test‑pattern error counter.

The test-pattern check uses the following register fields:

  1. Bit 1 of the TEST_MODE register at offset 0x019 enables the RX test-pattern mode.
  2. The TEST_PATTERN_COUNTER register at offset 0x01A , a 32‑bit register that saturates, counts the number of mismatched blocks when the IP core is in test-pattern mode.
  3. Bit 2 of the TEST_MODE register enables software to clear the test-pattern error counter.