40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.4.2.1. PMD Registers

Table 67.  PMD Control and Status RegistersThe physical medium dependent (PMD) control and status registers allow you to turn on and determine the status of the PMD device in the 40-100GbE IP core example design.

Address

Name

Bits

Description

HW Reset Value

Access

0x400

PMD_VERSION

[31:0]

PMD revision. The character string is “OPTs.”

0x4F505473

R

0x401

SCRATCH_PMD

[31:0]

Scratch register available for testing.

0x00000000

RW

0x402

PMD_CMD_CONFIG

[0]

Writing a 1 enables the PMD. When you set this register to the value of 1, the IP core seeks RX lock.

0x00000000

RW

0x403

CMD_STATUS

[6]

PMD global alarm.

1b’0

R

[5]

Programmable alarm 3. Defaults to module ready.

1b’0

R

[4]

Programmable alarm 2. Defaults to high power mode on.

1b’0

R

[3]

Programmable alarm 1. Defaults to RX CDR lock.

1b’0

R

[2]

RX side signal detected.

1’b0

R

[1]

When asserted, the PMD module is physically plugged in. When deasserted, it is offline.

1b’1

R

[0]

When 1, the PMD is resetting. When 0, the PMD is available.

1’b1

R