40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

1.4.1. Resource Utilization for 40GbE IP Cores

Resource utilization changes if the statistics counters are configured in the IP core. You can specify whether to include or not include the statistics counters in the 40-100GbE parameter editor, but you cannot change the setting dynamically.

The 24.24 Gbps variations of the 40-100GbE IP core use the same resources as the standard 40GbE IP core variations. The 40GBASE-KR4 variations require more resources only for the PHY component.

Table 4.  40GbE IP Core FPGA Resource Utilization in Stratix V and Arria V GZ Devices Lists the resources and expected performance for selected variations of the 40GbE IP cores in an Arria V GZ or Stratix V device. The results were obtained using the Quartus II software v13.1 for a Stratix V 5SGXEA7N2F45C2 device.
  • Top-level modules are in bold.
  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.

Module

ALMs

Logic Registers

Memory

M20K

MAC&PHY with Avalon-ST client interface without statistics counters

13600

23500

9

MAC&PHY with Avalon-ST client interface and with statistics counters

17700

30900

9

MAC with Avalon-ST client interface without statistics counters

7100

15000

9

MAC with Avalon-ST client interface and with statistics counters

11300

22300

9

  • alt_e40_adapter_rx:adapter_rx

500

900

0

  • alt_e40_adapter_tx:adapter_tx

300

700

0

MAC with custom streaming client interface without statistics counters

6200

13400

9

MAC with custom streaming client interface and with statistics counters

10400

20700

9

  • alt_e40_mac_rx:mac_rx

3000

7000

9

  • alt_e40_mac_tx:mac_tx

2600

4800

0

  • alt_e40_mac_csr:mac_csr without statistics counters

700

2000

0

  • alt_e40_mac_csr:mac_csr with statistics counters

4600

8500

0

PHY

6800

8600

0

  • alt_e40_phy_pcs:phy_pcs

6200

8200

0

    • alt_e40_pcs_rx:pcs_rx

2800

3800

0

    • alt_e40_pcs_tx:pcs_tx

2900

3300

0

    • alt_e40_phy_csr:phy_csr

500

1100

0

  • alt_e40_phy_pma:phy_pma

200

400

0

40GBASE-KR4 PHY

  • No auto-negotiation (AN)
  • No link training (LT)
  • Forward error correction (FEC) only
  • Use M20K blocks for FEC buffer

14800

16700

8

40GBASE-KR4 PHY

  • AN
  • LT
  • FEC
  • Use M20K blocks for FEC buffer

23800

24500

8

40GBASE-KR4 PHY

  • AN
  • LT
  • FEC
  • Do not use M20K blocks for FEC buffer

31900

41600

0

Table 5.  40GbE IP Core FPGA Resource Utilization in Stratix IV Devices Lists the resources and expected performance for selected variations of the 40GbE IP cores in a Stratix IV device. The results were obtained using the Quartus II software v13.1 for a Stratix IV EP4S100G5F45C2 device.
  • Top-level modules are in bold.
  • The numbers of ALMs and logic registers are rounded up to the nearest 100.

Module

ALMs

Logic Registers

Memory

M9K

MAC&PHY with Avalon-ST client interface without statistics counters

18100

25000

20

MAC&PHY with Avalon-ST client interface and with statistics counters

22100

32100

20

MAC with Avalon-ST client interface without statistics counters

9700

15200

20

MAC with Avalon-ST client interface and with statistics counters

13700

22200

20

  • alt_e40_adapter_rx:adapter_rx

700

1000

0

  • alt_e40_adapter_tx:adapter_tx

500

800

0

MAC with custom streaming client interface without statistics counters

8500

13400

20

MAC with custom streaming client interface and with statistics counters

12500

20400

20

  • alt_e40_mac_rx:mac_rx

4300

7000

20

  • alt_e40_mac_tx:mac_tx

3400

4800

0

  • alt_e40_mac_csr:mac_csr without statistics counters

1400

1900

0

  • alt_e40_mac_csr:mac_csr with statistics counters

5000

8300

0

PHY

8600

9900

0

  • alt_e40_phy_pcs:phy_pcs

8100

9400

0

    • alt_e40_pcs_rx:pcs_rx

3700

4400

0

    • alt_e40_pcs_tx:pcs_tx

3600

3900

0

    • alt_e40_phy_csr:phy_csr

700

1100

0

  • alt_e40_phy_pma_siv:pma

600

500

0