40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.2.17.1. PCS BER Monitor

The PCS implements bit error rate (BER) monitoring as specified by the IEEE 802.3ba-2010 100G Ethernet Standard. When the PCS deskews the data and aligns the lanes, the BER monitor checks the signal quality and asserts hi_ber if it detects excessive errors. When align_status is asserted and hi_ber is deasserted, the RX PCS continuously accepts blocks and generates RXD <63:0> and RXC <7:0> on the XLGMII or CGMII interface.

High BER occurs when 97 invalid 66-bit synchronous headers are detected for 100GbE within 500 µs or detected for 40GbE within 1.25 ms. When fewer than 97 invalid 66-bit synchronous headers occur in the same window, the IP core exists the high BER state.

For more information, refer to Figure 82–13—BER monitor state diagram illustrated in the IEEE 802.3ba-2010 100G Ethernet Standard.