40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
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Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

C.1. 10GBASE-KR PHY Register Definitions

The Avalon-MM master interface signals provide access to the control and status registers.
The following table specifies the control and status registers that you can access over the Avalon‑MM PHY management interface. A single address space provides access to all registers.
Note:
  • Unless otherwise indicated, the default value of all registers is 0.
  • Writing to reserved or undefined register addresses may have undefined side effects.
  • To avoid any unspecified bits to be erroneously overwritten, you must perform read-modify-writes to change the register values.
Table 72.  10GBASE-KR Register Definitions
Word Addr Bit R/W Name Description
0xB0 0 RW Reset SEQ When set to 1, resets the 10GBASE‑KR sequencer, initiates a PCS reconfiguration, and may restart Auto-Negotiation, Link Training or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
1 RW Disable AN Timer Auto‑Negotiation disable timer. If disabled ( Disable AN Timer = 1) , AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature. In addition, software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state. To enable this timer set Disable AN Timer = 0.
2 RW Disable LF Timer When set to 1, disables the Link Fault timer. When set to 0, the Link Fault timer is enabled.
6:4 RW SEQ Force Mode[2:0]

Forces the sequencer to a specific protocol. Must write the Reset SEQ bit to 1 for the Force to take effect. The following encodings are defined:

  • 3'b000: No force
  • 3'b001: GigE
  • 3'b010: Reserved
  • 3'b011: Reserved
  • 3'b100: 10GBASE-R
  • 3'b101: 10GBASE‑KR
  • Others: Reserved
16 RW Assert KR FEC Ability When set to 1, indicates that the FEC ability is supported. This bit defaults to 1 if the Set FEC_ability bit on power up/reset bit is on. For more information, refer to the FEC variable FEC_Enable as defined in Clause 74.8.2 and 10GBASE-KR PMD control register bit (1.171.0) IEEE 802.3ap-2007.
17 RW Enable KR FEC Error Indication When set to 1, the FEC module indicates errors to the 10G PCS. For more information, refer to the KR FEC variable FEC_enable_Error_to_PCS and 10GBASE-KR PMD control register bit (1.171.1) as defined in Clause 74.8.3 of IEEE 302.3ap-2007.
18 RW Assert KR FEC Request When set to 1, indicates that the core is requesting the FEC ability. When this bit changes, you must assert the Reset SEQ bit (0xB0[0]) to renegotiate with the new value.
0xB1 0 R SEQ Link Ready When asserted, the sequencer is indicating that the link is ready.
1 R SEQ AN timeout When asserted, the sequencer has had an Auto‑Negotiation timeout. This bit is latched and is reset when the sequencer restarts Auto‑Negotiation.
2 R SEQ LT timeout When set, indicates that the Sequencer has had a timeout.
13:8 R SEQ Reconfig Mode[5:0] Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined:
  • Bit 8, mode[0]: AN mode
  • Bit 9, mode[1]: LT Mode
  • Bit 10, mode[2]: 10G data mode
  • Bit 11, mode[3]: Gige data mode
  • Bit 12, mode[4]: Reserved for XAUI
  • Bit13, mode[5]: 10G FEC mode
16 R KR FEC Ability Indicates whether or not the 10GBASE-KR PHY supports FEC. For more information, refer to the FEC variable FEC_Enable as defined in Clause 74.8.2 and 10GBASE-KR PMD control register bit (1.171.0) IEEE 802.3ap-2007.
17 R Enable KR FEC Error Indication Ability When set to 1, indicates that the 10GBASE-KR PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to the KR FEC variable FEC_enable_Error_to_PCS and 10GBASE-KR PMD control register bit (1.171.1) as defined in Clause 74.8.3 of IEEE 302.3ap-2007.
0xB2 0 RW FEC TX trans error When asserted, indicates that the error insertion feature in the FEC Transcoder is enabled.
1 RW FEC TX burst error When asserted, indicates that the error insertion feature in the FEC Encoder is enabled.
5:2 RW FEC TX burst length Specifies the length of the error burst. Values 1-16 are available.
10:6 Reserved
11 RWSC FEC TX Error Insert Writing a 1 inserts 1 error pulse into the TX FEC depending on the Transcoder and Burst error settings. Software clears this register.
31:15 RWSC Reserved
0xB3 31:0 RSC FEC Corrected Blocks Counts the number of corrected FEC blocks. Resets to 0 when read. Otherwise, it holds at the maximum count and does not roll over. Refer to Clause 74.8.4.1 of IEEE 802.3ap-2000 for details.
0xB4 31:0 RSC FEC Uncorrected Blocks Counts the number of uncorrectable FEC blocks. Resets to 0 when read. Otherwise, it holds at the maximum count and does not roll over. Refer to Clause 74.8.4.1 of IEEE 802.3ap-2000 for details.
0xC0 0 RW AN enable When set to 1, enables Auto‑Negotiation function. The default value is 1. For additional information, refer to bit 7.0.12 in Clause 73.8 Management Register Requirements, of IEEE 802.3ap‑2007.
1 RW AN base pages ctrl When set to 1, the user base pages are enabled. You can send any arbitrary data via the user base page low/high bits. When set to 0, the user base pages are disabled and the state machine generates the base pages to send.
2 RW AN next pages ctrl When set to 1, the user next pages are enabled. You can send any arbitrary data via the user next page low/high bits. When set to 0, the user next pages are disabled. The state machine generates the null message to send as next pages.
3 R Local device remote fault When set to 1, the local device signals Remote Faults in the Auto‑Negotiation pages. When set to 0 a fault has not occurred.
4 RW Force TX nonce value When set to 1, forces the TX none value to support some UNH-IOL testing modes. When set to 0, operates normally.
5 RW Override AN When set to 1, the override settings defined by the AN_TECH, AN_FEC and AN_PAUSE registers take effect.
0xC1 0 RW Reset AN When set to 1, resets all the 10GBASE‑KR Auto‑Negotiation state machines. This bit is self-clearing.
4 RW Restart AN TX SM When set to 1, restarts the 10GBASE‑KR TX state machine. This bit self clears. This bit is active only when the TX state machine is in the AN state. For more information, refer to bit 7.0.9 in Clause 73.8 Management Register Requirements of IEEE 802.3ap‑2007.
8 RW AN Next Page When asserted, new next page info is ready to send. The data is in the XNP TX registers. When 0, the TX interface sends null pages. This bit self clears. Next Page (NP) is encoded in bit D15 of Link Codeword. For more information, refer to Clause 73.6.9 and bit 7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap‑2007.
0xC2 1 RO AN page received When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE 802.3ap‑2007.
2 RO AN Complete When asserted, Auto‑Negotiation has completed. When 0, Auto‑Negotiation is in progress. For more information, refer to bit 7.1.5 in Clause 73.8 of IEEE 802.3ap‑2007.
3 RO AN ADV Remote Fault When set to 1, fault information has been sent to the link partner. When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. For more information, refer to Clause 73.6.7 of and bit 7.16.13 of IEEE 802.3ap‑2007.
4 RO AN RX SM Idle When set to 1, the Auto‑Negotiation state machine is in the idle state. Incoming data is not Clause 73 compatible. When 0, the Auto‑Negotiation is in progress.
5 RO AN Ability When set to 1, the transceiver PHY is able to perform Auto-Negotiation. When set to 0, the transceiver PHY i s not able to perform Auto-Negotiation. If your variant includes Auto‑Negotiation, this bit is tied to 1. For more information, refer to bits 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap‑2007.
6 RO AN Status When set to 1, link is up. When 0, the link is down. The current value clears when the register is read. For more information, refer to bit 7.1.2 of Clause 45 of IEEE 802.3ap‑2007.
7 RO LP AN Ability When set to 1, the link partner is able to perform Auto‑Negotiation. When 0, the link partner is not able to perform Auto-Negotiation. For more information, refer to bit 7.1.0 of Clause 45 of IEEE 802.3ap‑2007.
8 RO Enable FEC

When asserted, indicates that auto-negotiation is complete and that communicate includes FEC. For more information refer to Clause 7.48.4.

9 RO Seq AN Failure When set to 1, a sequencer Auto‑Negotiation failure has been detected. When set to 0, a Auto‑Negotiation failure has not been detected.
17:12 RO KR AN Link Ready[5:0] Provides a one-hot encoding of an_receive_idle = true and link status for the supported link as described in Clause 73.10.1. The following encodings are defined:
  • 6'b000000: 1000BASE-KX
  • 6'b000001: Reserved
  • 6'b000100: 10GBASE-KR
  • 6'b001000: Reserved
  • 6'b010000: Reserved
  • 6'b100000: Reserved
0xC3 15:0 RW User base page low The Auto‑Negotiation TX state machine uses these bits if the AN base pages ctrl bit is set. The following bits are defined:
  • [4:0]: Selector
  • [9:5]: Echoed nonce which are set by the state machine
  • [12:10]: Pause bits
  • [13]: Remote Fault bit
  • [14]: ACK which is controlled by the SM
  • [15]: Next page bit
Bit 49, the PRBS bit, is generated by the Auto‑Negotiation TX state machine.
21:16 RW Override AN_TECH[5:0]

Specifies an AN_TECH value to override. The following encodings are defined:

  • [16]: AN_TECH[0] = 1000Base-KX
  • [17]: AN_TECH[1] = XAUI
  • [18]: AN_TECH[2] = 10GBASE-KR
  • [19]: AN_TECH[3] = 40G
  • [20]: AN_TECH[4] = CR-4
  • [21]: AN_TECH[5] = 100G

You must write 0xC0[5] to 1'b1 for these overrides to take effect.

25:24 RW Override AN_FEC[1:0]
Specifies an AN_FEC value to override. The following encodings are defined:
  • [24]: AN_ FEC [0] = Capability
  • [25]: AN_ FEC [1] = Request

You must write 0xC0[5] to 1'b1 for these overrides to take effect.

30:28 RW Override AN_PAUSE[2:0]

Specifies an AN_PAUSE value to override. The following encodings are defined:

  • [28]: AN_PAUSE[0] = Pause Ability
  • [29]: AN_PAUSE[1] = Asymmetric Direction
  • [30]: AN_PAUSE[2] = Reserved

Need to set 0xC0 bit-5 to take effect.

0xC4 31:0 RW User base page high The Auto‑Negotiation TX state machine uses these bits if the Auto‑Negotiation base pages ctrl bit is set. The following bits are defined:
  • [4:0]: Correspond to bits 20:16 which are TX nonce bits.
  • [29:5]: Correspond to page bit 45:21 which are the technology ability.
Bit 49, the PRBS bit, is generated by the Auto‑Negotiation TX state machine.
0xC5 15:0 RW User Next page low The Auto‑Negotiation TX state machine uses these bits if the Auto‑Negotiation next pages ctrl bit is set. The following bits are defined:
  • [11]: Toggle bit
  • [12]: ACK2 bit
  • [13]: Message Page (MP) bit
  • [14]: ACK controlled by the state machine
  • [15]: Next page bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap‑2007. Bit 49, the PRBS bit, is generated by the Auto‑Negotiation TX state machine.
0xC6 31:0 RW User Next page high The Auto‑Negotiation TX state machine uses these bits if the Auto‑Negotiation next pages ctrl bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the PRBS bit, is generated by the Auto‑Negotiation TX state machine.
0xC7 15:0 RO LP base page low The AN RX state machine received these bits from the link partner. The following bits are defined:
  • [4:0] Selector
  • [9:5] Echoed Nonce which are set by the state machine
  • [12:10] Pause bits
  • [12]: ACK2 bit
  • [13]: RF bit
  • [14]: ACK controlled by the state machine
  • [15]: Next page bit
0xC8 31:0 RO LP base page high The AN RX state machine received these bits from the link partner. The following bits are defined:
  • [31:30]: Reserved
  • [29:5]: Correspond to page bits [45:21] which are the technology ability
  • [4:0]: Correspond to bits [20:16] which are TX Nonce bits
0xC9 15:0 RO LP Next page low The AN RX state machine receives these bits from the link partner. The following bits are defined:
  • [15]: Next page bit
  • [14]: ACK which is controlled by the state machine
  • [13]: MP bit
  • [12] ACK2 bit
  • [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap‑2007.
0xCA 31:0 RO LP Next page high The AN RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16]
0xCB 24:0 RO AN LP ADV Tech_A[24:0] Received technology ability field bits of Clause 73 Auto‑Negotiation. The 10GBASE‑KR PHY supports A0 and A2. The following protocols are defined:
  • A0 1000BASE-KX
  • A1 10GBASE-KX4
  • A2 10GBASE-KR
  • A3 40GBASE-KR4
  • A4 40GBASE-CR4
  • A5 100GBASE-CR10
  • A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap‑2007.
26:25 RO AN LP ADV FEC_F[1:0] Received FEC ability bits. FEC [F0:F1] is encoded in bits D46:D47 of the base Link Codeword as described in Clause 73 AN, 73.6.5. Bit[26] corresponding to F1 is the request bit. Bit[25] corresponding to F0 is the FEC ability bit.
27 RO AN LP ADV Remote Fault Received Remote Fault (RF) ability bits. RF is encoded in bit D13 of the base link codeword in Clause 73 AN. For more information, refer to Clause 73.6.7 and bits AN LP base page ability register AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap‑2007.
30:28 RO AN LP ADV Pause Ability_C[2:0] Received pause ability bits. Pause (C0:C1) is encoded in bits D11:D10 of the base link codeword in Clause 73 AN as follows:
  • C0 is the same as PAUSE as defined in Annex 28B
  • C1 is the same as ASM_DIR as defined in Annex 28B
  • C2 is reserved
For more information, refer to bits AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap‑2007.
0xD0 0 RW Link Training enable When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR start-up protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.1) of IEEE 802.3ap‑2007.
1 RW dis_max_wait_tmr When set to 1, disables the LT max_wait_timer . Used for characterization mode when setting much longer BER timer values.
2 RW quick_mode When set to 1, only the init and preset values are used to calculate the best BER.
3 RW pass_one When set to 1, the BER algorithm considers more than the first local minimum when searching for the lowest BER. The default value is 1.
7:4 RW main_step_cnt [3:0] Specifies the number of equalization steps for each main tap update. There are about 20 settings for the internal algorithm to test. The valid range is 1-15. The default value is 4'b0010.
11:8 RW prpo_step_cnt [3:0] Specifies the number of equalization steps for each pre‑ and post‑ tap update. From 16-31 steps are possible. The default value is 4'b0001.
14:12 RW equal_cnt [2:0] Adds hysteresis to the error count to avoid local minimums. The default value is 3'b010. The following encodings are defined:
  • 3'b000: 0
  • 3'b001: 1
  • 3'b010: 2
  • 3'b100: 4
  • 3'b101: 8
  • 3'b110: 16
15 RW disable initialize PMA on max_wait_timeout

When set to 1, does not initialize the PMA VOD, pretap, posttap values upon entry into the Training_Failure state as defined in Figure 72-5 of Clause 72.6.10.4.3 of IEEE 802.3ap-2007. This failure occurs when the max_wait_timer_done timeout is reached setting the Link Training failure bit (0xD2[3]). Used during UNH-IOL testing.

When set to 0, initializes the PMA values upon entry into Training_Failure state.

16 RW Ovride LP Coef enable When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link Training logic to determine the link partner coefficients. Used with 0xD1 bit-4 and 0xD4 bits[7:0].
17 RW Ovride Local RX Coef enable When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0xD1 bit-8 and 0xD4 bits[23:16]. The default value is 1.
19:18 RMW Reserved

You should not modify these bits. To update this register, first read the value of this register then change only the value for bits that are not reserved.

22:20 RW rx_ctle_mode

RX CTLE mode in the Link Training algorithm. The default value is 3'b000. The following encodings are defined:

  • 3'b000: CTLE tuning in link training is disabled. Retains user set value of CTLE.
  • 3'b001: Reserved.
  • 3'b010: Reserved.
  • 3'b011: CTLE tuning in link training is enabled.
  • 3'b100 to 3'b111: reserved.
23 RW vod_up When set to 1, VOD is trained to high values. The default is set to 0 to save power and reduce crosstalk on the link.
26:24 RW rx_dfe_mode

RX DFE mode in the link training algorithm. The default value is 3'b000. The following bits are defined:

  • 3'b000: DFE adaptation in link training is disabled
  • 3'b001: Reserved
  • 3'b010: DFE is triggered at the end of link training
  • 3'b011: DFE is triggered at the end of VOD, Post tap and Pre-tap training
  • 3'b100 to 3'b111: Reserved
28 RW max_mode

When set to 1, link training operates in maximum TX equalization mode. Modifies the link training algorithm to settle on the max pretap and max VOD if the BER counter reaches the maximum for all values. Link training settles on the max_post_step for the posttap value.

31:29 RW max_post_step Number of TX posttap steps from the initialization state when in max_mode.
0xD1 0 RW Restart Link training When set to 1, resets the 10GBASE-KR start-up protocol. When set to 0, continues normal operation. This bit self clears. For more information, refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.0) IEEE 802.3ap‑2007.
4 RW Updated TX Coef new When set to 1, there are new link partner coefficients available to send. The LT logic starts sending the new values set in 0xD4 bits[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears. Must enable this override in 0xD0 bit16.
8 RW Updated RX coef new When set to 1, new local device coefficients are available. The LT logic changes the local TX equalizer coefficients as specified in 0xD4 bits[23:16]. When set to 0, continues normal operation. This bit self clears. Must enable the override in 0xD0 bit17.
0xD2 0 RO Link Trained - Receiver status When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress. For more information, refer to the state variable rx_trained as defined in Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control register bit 10GBASE_KR PMD status register bit (1.151.0) of IEEE 802.3ap‑2007.
1 RO Link Training Frame lock When set to 1, the training frame delineation has been detected. When set to 0, the training frame delineation has not been detected. For more information, refer to the state variable frame_lock as defined in Clause 72.6.10.3.1 and 10GBASE_KR PMD status register bit 10GBASE_KR PMD status register bit (1.151.1) of IEEE 802.3ap‑2007.
2 RO Link Training Start-up protocol status When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state training as defined in Clause 72.6.10.3.1 and 10GBASE_KR PMD status register bit (1.151.2) of IEEE 802.3ap‑2007.
3 RO Link Training failure When set to 1, a training failure has been detected. When set to 0, a training failure has not been detected For more information, refer to the state variable training_failure as defined in Clause 72.6.10.3.1 and bit 10GBASE_KR PMD status register bit (1.151.3) of IEEE 802.3ap‑2007.
4 RO Link Training Error When set to 1, excessive errors occurred during Link Training. When set to 0, the BER is acceptable.
5 RO Link Training Frame lock Error When set to 1, indicates a frame lock was lost during Link Training. If the tap settings specified by the fields of 0xD5 are the same as the initial parameter value, the frame lock error was unrecoverable.
6 RO CTLE Frame Lock Loss When set to 1, indicates that fram lock was lost at some point during CTLE link training.
7 RO CTLE Tuning Error When set to 1, indicates that CTLE did not achieve best results because the BER counter reached the maximum value for each step of CTLE tuning.
0xD3 9:0 RW ber_time_frames Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_frames is 0.The following values are defined:
  • A value of 2 is about 103 bytes
  • A value of 20 is about 104 bytes
  • A value of 200 is about 105 bytes
The default value for simulation is 2'b11. The default value for hardware is 0.
19:10 RW ber_time_k_frames Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames = 0 for time/bits to match the following values:
  • A value of 3 is about 10 7 bits = about 1.3 ms
  • A value of 25 is about 10 8 bits = about 11ms
  • A value of 250 is about 10 9 bits = about 11 0ms
The default value for simulation is 0. The default value for hardware is 0xF.
29:20 RW ber_time_m_frames Specifies the number of millions of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_k_frames = 4'd1000 = 0x3E8 for time/bits to match the following values:
  • A value of 3 is about 1010 bits = about 1.3 seconds
  • A value of 25 is about 10 11 bits = about 11 seconds
  • A value of 250 is about 1012 bits = about 110 seconds
The default value is 0x0.
0xD4 5:0 RO or RW LD coefficient update[5:0] Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read‑only; however, when you override training by setting the Ovride Coef enable control bit, these bits become writeable. The following fields are defined:
  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to bit 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE 802.3ap‑2007.
6 RO or RW LD Initialize Coefficients When set to 1, requests the link partner coefficients be set to configure the TX equalizer to its INITIALIZE state. When set to 0, continues normal operation. For more information, refer to 10G BASE-KR LD coefficient update register bits (1.154.12) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap‑2007.
7 RO or RW LD Preset Coefficients When set to 1, requests the link partner coefficients be set to a state where equalization is turned off. When set to 0 the link operates normally. For more information, refer to bit 10G BASE-KR LD coefficient update register bit (1.154.13) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap‑2007.
13:8 RO LD coefficient status[5:0] Status report register for the contents of the second, 16‑bit word of the training frame most recently sent from the local device control channel. The following fields are defined:
  • [5:4]: Coefficient (post‑tap)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • [1:0]: Coefficient (pre‑tap) (same encoding as [5:4])
For more information, refer to bit 10G BASE-KR LD status report register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE 802.3ap‑2007.
14 RO Link Training ready - LD Receiver ready When set to 1, the local device receiver has determined that training is complete and is prepared to receive data. When set to 0, the local device receiver is requesting that training continue. Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information refer to For more information, refer to bit 10G BASE-KR LD status report register bit (1.155.15) in Clause 45.2.1.81 of IEEE 802.3ap‑2007.
21:16 RO or RW LP coefficient update[5:0] Reflects the contents of the first 16-bit word of the training frame most recently received from the control channel.
Normally the bits in this register are read only; however, when training is disabled by setting low the KR Training enable control bit, these bits become writeable. The following fields are defined:
  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to bit 10G BASE-KR LP coefficient update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE 802.3ap‑2007.
22 RO or RW LP Initialize Coefficients When set to 1, the local device transmit equalizer coefficients are set to the INITIALIZE state. When set to 0, normal operation continues. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to bit 10G BASE-KR LP coefficient update register bits (1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap‑2007.
23 RO or RW LP Preset Coefficients When set to 1, The local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The function and values of the preset bit is defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to bit 10G BASE-KR LP coefficient update register bits (1.152.13) in Clause 45.2.1.78.3 of IEEE 802.3ap‑2007.
29:24 RO LP coefficient status[5:0] Status report register reflects the contents of the second, 16-bit word of the training frame most recently received from the control channel: The following fields are defined:
  • [5:4]: Coefficient (+1)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to bit 10G BASE-KR LP status report register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE 802.3ap‑2007.
30 RO LP Receiver ready When set to 1, the link partner receiver has determined that training is complete and is prepared to receive data. When set to 0, the link partner receiver is requesting that training continue.

Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to bit 10G BASE-KR LP status report register bits (1.153.15) in Clause 45.2.1.79 of IEEE 802.3ap‑2007.

0xD5 5:0 R LT VOD setting Stores the most recent VOD setting that LT specified using the Transceiver Reconfiguration Controller IP core. It reflects Link Partner commands to fine‑tune the VOD.
12:8 R LT Post-tap setting Stores the most recent post‑tap setting that LT specified using the Transceiver Reconfiguration Controller IP core. It reflects Link Partner commands to fine‑tune the TX pre‑emphasis taps.
19:16 R LT Pre-tap setting Stores the most recent pre-tap setting that LT specified using the Transceiver Reconfiguration Controller IP core. It reflects Link Partner commands to fine‑tune the TX pre‑emphasis taps.
23:20 R RXEQ CTLE Setting Stores the most recent CTLE setting sent to the Transceiver Reconfiguration IP Core during RX Equalization.
25:24 R RXEQ CTLE Mode Stores the most recent CTLE mode that CTLE specified using the Transceiver Reconfiguration IP Core during RX Equalization.
27:26 R RXEQ DFE Mode Stores the most recent DFE setting sent to the Transceiver Reconfiguration IP Core during RX Equalization.
0xD6 5:0 RW LT VODMAX ovrd Override value for the VMAXRULE parameter. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only effects the local device TX output for the channel specified.

This value must be greater than the INITMAINVAL parameter for proper operation. Note this will also override the PREMAINVAL parameter value.

6 RW LT VODMAX ovrd Enable When set to 1, enables the override value for the VMAXRULE parameter stored in the LT VODMAX ovrd register field.
13:8 RW LT VODMin ovrd Override value for the VODMINRULE parameter. When enabled, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be less than the INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation.

14 RW LT VODMin ovrd Enable When set to 1, enables the override value for the VODMINRULE parameter stored in the LT VODMin ovrd register field.
20:16 RW LT VPOST ovrd Override value for the VPOSTRULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation.

21 RW LT VPOST ovrd Enable When set to 1, enables the override value for the VPOSTRULE parameter stored in the LT VPOST ovrd register field.
27:24 RW LT VPre ovrd Override value for the VPRERULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value greater than the INITPREVAL parameter for proper operation.

28 RW LT VPre ovrd Enable When set to 1, enables the override value for the VPRERULE parameter stored in the LT VPre ovrd register field.
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