40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
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Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

3.4.1.12. 40GBASE-KR4 Registers

Most 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the 10GBASE-KR PHY IP core, documented in the Altera Transceiver PHY IP Core User Guide. The register offsets are identical in the 40GBASE-KR4 variations of the 40-100GbE IP core. However, the 40GBASE-KR4 variations of the 40-100GbE IP core have additional 40GBASE-KR4 related registers and register fields.

For your convenience, the 40-100GbE IP core user guide includes an appendix with the 10GBASE-KR PHY register descriptions: 10GBASE-KR Registers.

Table 57.  40-100GbE IP Core 40GBASE-KR4 Registers and Register Fields Not in 10GBASE-KR PHY IP Core

Documents the differences between the 10GBASE-KR PHY register definitions and the 40GBASE-KR4 registers of the 40-100GbE IP core. All 10GBASE-KR PHY registers and register fields not listed in the table are available in the 40GBASE-KR4 variations of the 40-100GbE IP core.

The 10GBASE-KR PHY register listings are available in the 10GBASE-KR Registers appendix and in the 10GBASE-KR PHY Register Defintions section of the Backplane Ethernet 10GBASE-KR PHY IP Core with FEC Option chapter of the Altera Transceiver PHY IP Core User Guide. The information in these two sources should be identical. Refer to 10GBASE-KR Registers for details.

Where the 10GBASE-KR PHY register definitions list 10GBASE-R, substitute 40GBASE-KR4 with auto-negotiation and link training both turned off, and where the 10GBASE-KR PHY register definitions list 10GBASE-KR (except in the description of 0xCB[24:0]), substitute 40GBASE-KR4. Where a register field description in the 10GBASE-KR PHY register definitions refers to link training or FEC in the single-lane 10GBASE-KR PHY IP core, substitute link training or FEC on Lane 0 of the 40GBASE-KR4 IP core variation. Where a register field description in the 10GBASE-KR PHY register definitions refers to the Transceiver Reconfiguration IP core, substitute the reconfiguration bundle.

To modify a field value in any 40GBASE-KR4 specific register, whether an underlying 10GBASE-KR PHY IP core register or one of the registers defined in this table, you must perform a read-modify-write operation to ensure you do not modify the values of any other fields in the register.

Address

Name

Bit

Description

HW Reset Value

Access

0x0B0

Force Negotiate to FEC Mode

[19]

When set to 1, forces the IP core to use FEC mode regardless of the auto-negotiation result. You must write the value of 1 to 0xB0[0] (reset the sequencer) for this override to take effect.

1’b0

RW

FEC Block Lock

[23:20]

FEC Block Lock for lanes [3:0]: bit [20] is FEC block lock for lane 0, bit [21] is FEC block lock for lane 1, bit [22] is FEC block lock for lane 2, and bit [23] is FEC block lock for lane 3.

4’b0

RO

0x0B5

Register 0xB2 refers to Lane 0. This register is the equivalent of register 0xB2 for Lane 1. (Refer to 0xB2).

RW

0x0B6

KR4 FEC Corrected Blocks, Lane 1 [31:0]

Maintains count of corrected FEC blocks on Lane 1, saturating (not rolling over) at 232-1. Resets to 0 when read. Refer to Clause 74.8.4.1 of IEEE Std 802.3ap-2007.

32'b0

RO

0x0B7

KR4 FEC Uncorrected Blocks, Lane 1 [31:0]

Maintains count of uncorrected (uncorrectable) FEC blocks on Lane 1, saturating (not rolling over) at 232-1. Resets to 0 when read. Refer to Clause 74.8.4.2 of IEEE Std 802.3ap-2007.

32'b0

RO

0x0B8

This register is the equivalent of register 0xB2 for Lane 2. (Refer to 0xB2).

RW

0x0B9

KR4 FEC Corrected Blocks, Lane 2 [31:0]

Maintains count of corrected FEC blocks on Lane 2, saturating (not rolling over) at 232-1. Resets to 0 when read. Refer to Clause 74.8.4.1 of IEEE Std 802.3ap-2007.

32'b0

RO

0x0BA

KR4 FEC Uncorrected Blocks, Lane 2 [31:0]

Maintains count of uncorrected (uncorrectable) FEC blocks on Lane 2, saturating (not rolling over) at 232-1. Resets to 0 when read. Refer to Clause 74.8.4.2 of IEEE Std 802.3ap-2007.

32'b0

RO

0x0BB

This register is the equivalent of register 0xB2 for Lane 3. (Refer to 0xB2).

RW

0x0BC

KR4 FEC Corrected Blocks, Lane 3 [31:0]

Maintains count of corrected FEC blocks on Lane 3, saturating (not rolling over) at 232-1. Resets to 0 when read. Refer to Clause 74.8.4.1 of IEEE Std 802.3ap-2007.

32'b0

RO

0x0BD

KR4 FEC Uncorrected Blocks, Lane 3 [31:0]

Maintains count of uncorrected FEC blocks on Lane 3, saturating (not rolling over) at 232-1. Resets to 0 when read. Refer to Clause 74.8.4.2 of IEEE Std 802.3ap-2007.

32'b0

RO

0x0C0

Override AN Channel Enable [6]

Overrides the auto-negotiation master channel that you set with the Auto-Negotiation Master parameter, setting the new master channel according to the value in register 0xCC[3:0].

While 0x0C0[6] has the value of 1, the channel encoded in 0xCC[3:0] is the master channel. While 0xC0[6] has the value of 0, the master channel is the channel that you set with the Auto-Negotiation Master parameter.

1'b0

RW

0x0CB

AN LP ADV FEC_F[1:0] [26:25]

Received FEC ability bits. Bit [26] is FEC requested and bit [25] is FEC ability. FEC (F0:F1) is encoded in bits D46:D47 of the base Link Codeword in Clause 73 AN. F0 is FEC ability and F1 is FEC requested. Refer to Clause 73.6.5 of IEEE Std 802.3ap-2007.

2'b0

RO

0x0CC

Override AN Channel Select [3:0]

If you set the value of the Override AN Channel Enable register field (0xC0[6]) to the value of 1, then while 0xC0[6] has the value of 1, the value in this register field (0xCC[3:0])overrides the master channel you set with the Auto-Negotiation Master parameter.

This register field has the following valid values:

  • 4'b0001: Selects Lane 0
  • 4'b0010: Selects Lane 1
  • 4'b0100: Selects Lane 2
  • 4'b1000: Selects Lane 3

All other values are invalid. The new master channel is encoded with one-hot encoding.

4'b0

RW

0x0D1

Restart Link training, Lane 1 [1]

When set to 1, resets the 40GBASE-KR4 start-up protocol. When set to 0, continues normal operation. This bit self clears. Refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.0) in IEEE Std 802.3ap-2007.

Register bit 0xD1[0] refers to Lane 0. This bit is the equivalent of register 0xD1[0] for Lane 1. (Refer to 0xD1[0]).

1'b0

RW

Restart Link training, Lane 2 [2]

This bit is the equivalent of register 0xD1[0] for Lane 2. (Refer to 0xD1[0]).

1'b0

RW

Restart Link training, Lane 3 [3]

This bit is the equivalent of register 0xD0[1] for Lane 3. (Refer to 0xD1[0]).

1'b0

RW

0x0D1

Updated TX Coef new, Lane 1 [5]

When set to 1, indicates that new link partner coefficients are available to send. The LT logic starts sending the new values set in 0xD4[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[16] (Ovride LP Coef enable) has the value of 1. If 0xD0[16] has the value of 0, this register field (0xD1[5]) has no effect.

Register bit 0xD1[4] refers to Lane 0. This bit is the equivalent of register 0xD1[4] for Lane 1. (Refer to 0xD1[4]).

1'b0

RW

Updated TX Coef new, Lane 2 [6]

This bit is the equivalent of register 0xD1[5] for Lane 2.

1'b0

RW

Updated TX Coef new, Lane 3 [7]

This bit is the equivalent of register 0xD1[5] for Lane 3.

1'b0

RW

0x0D1

Updated RX Coef new, Lane 1 [9]

When set to 1, indicates that new local device coefficients are available for Lane 1. The LT logic changes the local TX equalizer coefficients as specified in 0xE1[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1. If 0xD0[17] has the value of 0, this register field (0xD1[9]) has no effect.

Register bit 0xD1[8] refers to Lane 0. This bit is the equivalent of register 0xD1[8] for Lane 1. (Refer to 0xD1[8]).

1'b0

RW

Updated RX Coef new, Lane 2 [10]

When set to 1, indicates that new local device coefficients are available for Lane 2. The LT logic changes the local TX equalizer coefficients as specified in 0xE5[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1.

This bit is the equivalent of register 0xD1[9] for Lane 2.

1'b0

RW

Updated RX Coef new, Lane 3 [11]

When set to 1, indicates that new local device coefficients are available for lane 3. The LT logic changes the local TX equalizer coefficients as specified in 0xE9[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1.

This bit is the equivalent of register 0xD1[9] for Lane 3.

1'b0

RW

0xD2

[15:8]

Register bits 0xD2[7:0] refer to Lane 0. These bits are the equivalent of 0xD2[7:0] for Lane 1. (Refer to 0xD2[7:0]).

For Link Training Frame lock Error, Lane 1, if the tap settings specified by the fields of 0xE2 are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

[23:16]

These bits are the equivalent of 0xD2[7:0] for Lane 2. (Refer to 0xD2[7:0]).

For Link Training Frame lock Error, Lane 2, if the tap settings specified by the fields of 0xE6 are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

[31:24]

These bits are the equivalent of 0xD2[7:0] for Lane 3. (Refer to 0xD2[7:0]).

For Link Training Frame lock Error, Lane 3, if the tap settings specified by the fields of 0xEA are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

0xE0

Register 0xD3 refers to Lane 0. This register, register 0xE0, is the equivalent of register 0xD3 for Lane 1 link training. (Refer to 0xD3).

RW

0xE1

Register 0xD4 refers to Lane 0. This register, register 0xE1, is the equivalent of register 0xD4 for Lane 1 link training. (Refer to 0xD4).

RW

0xE2

Register 0xD5 refers to Lane 0. This register, register 0xE2, is the equivalent of register 0xD5 for Lane 1 link training. (Refer to 0xD5).

RO

0xE3

Register 0xD6 refers to Lane 0. This register, register 0xE3, is the equivalent of register 0xD6 for Lane 1 link training. (Refer to 0xD6).

RW

0xE4

This register is the equivalent of register 0xD3 for Lane 2 link training. (Refer to 0xD3).

RW

0xE5

This register is the equivalent of register 0xD4 for Lane 2 link training. (Refer to 0xD4).

R / RW

0xE6

This register is the equivalent of register 0xD5 for Lane 2 link training. (Refer to 0xD5).

RO

0xE7

This register is the equivalent of register 0xD6 for Lane 2 link training. (Refer to 0xD6).

RW

0xE8

This register is the equivalent of register 0xD3 for Lane 3 link training.

RW

0xE9

This register is the equivalent of register 0xD4 for Lane 3 link training.

R / RW

0xEA

This register is the equivalent of register 0xD5 for Lane 3 link training.

RO

0xEB

This register is the equivalent of register 0xD6 for Lane 3 link training.

RW

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